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| ISP1581 Universal Serial Bus 2.0 high-speed interface device Rev. 04 -- 18 July 2002 Product data 1. General description The ISP1581 is a cost-optimized and feature-optimized Universal Serial Bus (USB) interface device, which fully complies with the Universal Serial Bus Specification Rev. 2.0. It provides high-speed USB communication capacity to systems based on a microcontroller or microprocessor. The ISP1581 communicates with the system's microcontroller/processor through a high-speed general-purpose parallel interface. The ISP1581 supports automatic detection of USB 2.0 system operation. The USB 1.1 fall-back mode allows the device to remain operational under full-speed conditions. It is designed as a generic USB interface device so that it can fit into all existing device classes, such as: Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices and Human Interface Devices. The internal generic DMA block allows easy integration into data streaming applications. In addition, the various configurations of the DMA block are tailored for mass storage applications. The modular approach to implementing a USB interface device allows the designer to select the optimum system microcontroller from the wide variety available. The ability to re-use existing architecture and firmware investments shortens the development time, eliminates risk and reduces costs. The result is fast and efficient development of the most cost-effective USB peripheral solution. The ISP1581 is ideally suited for many types of peripherals, such as: printers; scanners; magneto-optical (MO), compact disc (CD), digital video disc (DVD) and Zip(R)/Jaz(R) drives; digital still cameras; USB-to-Ethernet links; cable and DSL modems. The low power consumption during `suspend' mode allows easy design of equipment that is compliant to the ACPITM, OnNowTM and USB power management requirements. The ISP1581 also incorporates features such as SoftConnectTM, a reduced frequency crystal oscillator and integrated termination resistors. These features allow significant cost savings in system design and easy implementation of advanced USB functionality into PC peripherals. Philips Semiconductors ISP1581 USB 2.0 HS interface device 2. Features s s s s s s s s s s s s s s s s s s s Direct interface to ATA/ATAPI peripherals Complies fully with Universal Serial Bus Specification Rev. 2.0 Complies with most Device Class specifications High performance USB interface device with integrated Serial Interface Engine (SIE), PIE, FIFO memory, data transceiver and 3.3 V voltage regulators Supports automatic USB 2.0 mode detection and USB 1.1 fall-back mode High speed DMA interface Fully autonomous and multi-configuration DMA operation 7 IN endpoints, 7 OUT endpoints and a fixed control IN/OUT endpoint Integrated physical 8 kbyte of multi-configuration FIFO memory Endpoints with double buffering to increase throughput and ease real-time data transfer Bus independent interface with most microcontroller/microprocessors (15 Mbytes/s or 15 Mwords/s) 12 MHz crystal oscillator with integrated PLL for low EMI Integrated 5 V to 3 V built-in voltage regulator Software controlled connection to the USB bus (SoftConnectTM) Complies with the ACPITM, OnNowTM and USB power management requirements Internal power-on and low-voltage reset circuit, also supporting a software reset Operation over the extended USB bus voltage range (4.0 to 5.5 V) with 5 V tolerant I/O pads Operating temperature range -40 to +85 C Available in LQFP64 package. 3. Applications s s s s s s s s s Personal Digital Assistant (PDA) Mass storage device, e.g., Zip(R), Jaz(R), MO, CD, DVD drive Digital Video Camera Digital Still Camera 3G mobile phone MP3 player Communication device, e.g. router, modem Printer Scanner. 4. Ordering information Table 1: Ordering information Package Name ISP1581BD LQFP64 Description Plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm Version SOT314-2 Type number 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 2 of 80 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data Rev. 04 -- 18 July 2002 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09665 5. Block diagram Philips Semiconductors to/from USB D+ D- 12 MHz CS0, CS1, DA0*, DA1*, DA2 5 18, 17, 19, 20, 21 DMA HANDLER DREQ, DACK, DIOR, DIOW 4 12, 13, 14, 15 11 16 EOT INTRQ IORDY* XTAL1 6 5 60 XTAL2 59 3.3 V 1.5 k RPU 7 SoftConnect PHILIPS SIE/PIE USB 2.0 TRANSCEIVER DMA INTERFACE 22 40, 41, 44 to 57 MEMORY MANAGEMENT UNIT 19 DMA REGISTERS 20, 9 16 DATA0 to DATA15 BUS_CONF* 2 MODE0*, MODE1 RREF 8 12.0 k 22 INTEGRATED RAM (8 KBYTE) MICROCONTROLLER HANDLER MICRO CONTROLLER INTERFACE 30 to 35, 38, 39 25, 29, 26, 27 8 READY* AD0 to AD7 4 CS, ALE/A0, (R/W)/RD, DS/WR INT RESET 10 POWER-ON RESET internal reset 3.3 V VCC(5.0) 2 5V VOLTAGE REGULATORS 3.3 V digital supply analog supply 24, 37, 43, 58, 64 5 28 SYSTEM CONTROLLER ISP1581 1, 23, 36, 42, 61 5 DGND 3 1 AGND 4 63 62 004aaa153 VCC(3.3) TEST WAKEUP *Denotes shared pin usage USB 2.0 HS interface device VCCA(3.3) ISP1581 The direction of pins DREQ, DACK, DIOR and DIOW is determined by bit MASTER (DMA Hardware register) and bit ATA_MODE (DMA Configuration register). Fig 1. Block diagram. 3 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 6. Pinning information 6.1 Pinning 62 WAKEUP 64 VCC(3.3) 58 VCC(3.3) 57 DATA15 56 DATA14 55 DATA13 54 DATA12 53 DATA11 52 DATA10 width 51 DATA9 50 DATA8 60 XTAL1 DGND 1 VCC(5.0) 2 AGND 3 VCCA(3.3) 4 D- D+ 59 XTAL2 61 DGND 63 TEST 49 DATA7 48 DATA6 47 DATA5 46 DATA4 45 DATA3 44 DATA2 43 VCC(3.3) 42 DGND 41 DATA1 5 6 RPU 7 RREF 8 ISP1581BD MODE1 9 RESET 10 EOT 11 DREQ 12 DACK 13 DIOR 14 DIOW 15 INTRQ 16 MODE0/DA1 20 DA2 21 READY/IORDY 22 DGND 23 VCC(3.3) 24 CS 25 (R/W)/RD 26 DS/ WR 27 INT 28 ALE/A0 29 AD0 30 AD1 31 CS1 17 CS0 18 BUS_CONF/DA0 19 AD2 32 40 DATA0 39 AD7 38 AD6 37 VCC(3.3) 36 DGND 35 AD5 34 AD4 33 AD3 MBL248 Fig 2. Pin configuration LQFP64. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 4 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 6.2 Pin description Table 2: Symbol[1] DGND VCC(5.0) [3] Pin description for LQFP64 Pin 1 2 Type[2] Description digital ground supply voltage (3.3 or 5.0 V). for 5.0 V operation, this is the only pin used. Refer to Section 10 AGND VCCA(3.3) [3] 3 4 - analog ground regulated supply voltage (3.3 V 0.3 V) from internal regulator; supplies internal analog circuits; used to connect decoupling capacitor and 1.5 k pull-up resistor on D+ line Remark: Cannot be used to supply external devices. Refer to Section 10 D- D+ RPU RREF MODE1 5 6 7 8 9 A A A A I USB D- connection (analog) USB D+ connection (analog) connection for external pull-up resistor for USB D+ line; must be connected to VCCA(3.3) via a 1.5 k resistor connection for external bias resistor; must be connected to ground via a 12.0 k ( 1%) resistor selects function of pin ALE/A0 (in Split Bus mode only): 0 -- ALE function (address latch enable) 1 -- A0 function (address/data indicator). input pad; TTL; 5 V tolerant. Remark: Connect to VCC(5.0) in Generic Processor mode. RESET 10 I reset input; TTL with Hysteresis; 5 V tolerant; a LOW level produces an asynchronous reset; connect to VCC for power-on reset (internal POR circuit) End Of Transfer input (programmable polarity, see Table 37); used in DMA slave mode only input pad; TTL; 5 V tolerant; 5 ns slew rate control. EOT 11 I DREQ 12 I/O DMA request (programmable polarity); direction depends on the bit MASTER in the DMA Hardware register (DMA master: input, DMA slave: output); see Table 35 and Table 36 bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DACK 13 I/O DMA acknowledge (programmable polarity); direction depends on bit MASTER in the DMA Hardware register (DMA slave: input, DMA master: output); see Table 35 and Table 36 bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 5 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Pin description for LQFP64 ...continued Pin 14 Type[2] I/O Description DMA read strobe (programmable polarity); direction depends on bit MASTER in the DMA Hardware register (DMA slave: input, DMA master: output); see Table 35 and Table 36 bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. Table 2: Symbol[1] DIOR DIOW 15 I/O DMA write strobe (programmable polarity); direction depends on bit MASTER in the DMA Hardware register (DMA slave: input, DMA master: output); see Table 35 and Table 36 bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. INTRQ CS1[5] CS0[5] BUS_CONF/ DA0[5] 16 17 18 19 I O O I/O interrupt request input from ATA/ATAPI peripheral; input pad; TTL with hysteresis; 5 V tolerant. chip select output for ATA/ATAPI device; CMOS output; 5 ns slew rate control; see Table 33 and Table 34 chip select output for ATA/ATAPI device; CMOS output; 5 ns slew rate control; see Table 33 and Table 34 during power-up: input to select the bus configuration 0 -- Split Bus mode; multiplexed 8-bit address/data bus on AD[7:0], separate DMA data bus on DATA[15:0][4] 1 -- Generic Processor mode; separate 8-bit address on AD[7:0], 16-bit processor data bus on DATA[15:0]. DMA is multiplexed on the processor bus as DATA[15:0]. normal operation: address output to select the task file register of an ATA/ATAPI device. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant; see Table 33 and Table 34 MODE0 DA1[5] 20 I/O during power-up: input to select the read/write strobe functionality in generic processor mode 0 -- Motorola style: pin 26 is R/W and pin 27 is DS 1 -- 8051 style: pin 26 is RD and pin 27 is WR normal operation: address output to select the task file register of an ATA/ATAPI device bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant; see Table 33 and Table 34 DA2[5] 21 O address output to select the task file register of an ATA/ATAPI device; CMOS output; 5 ns slew rate control; see Table 33 and Table 34 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 6 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Pin description for LQFP64 ...continued Pin 22 Type[2] I/O Description Generic processor mode: ready signal (READY; output) A LOW level signals that ISP1581 is processing a previous command or data and is not ready for the next command or data transfer; a HIGH level signals that ISP1581 is ready for the next microprocessor read or write. Split Bus mode: DMA ready signal (IORDY; input); used for accessing ATA/ATAPI peripherals (PIO and UDMA modes only). bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. Table 2: Symbol[1] READY/ IORDY DGND VCC(3.3) [3] 23 24 - digital ground supply voltage (3.3 V 0.3 V); supplies internal digital circuits or it is the tapped out voltage from the internal regulator; this regulated voltage cannot be used to drive external devices; see Section 10 chip select input; TTL; 5 V tolerant. input; function is determined by input MODE0 at power-up: MODE0 = 0 -- pin functions as R/W (Motorola style) MODE0 = 1 -- pin functions as RD (8051 style). input pad; TTL with hysteresis; 5 V tolerant. CS (R/W)/RD 25 26 I I DS/WR 27 I input; function is determined by input MODE0 at power-up: MODE0 = 0 -- pin functions as DS (Motorola style) MODE0 = 1 -- pin functions as WR (8051 style). input pad; TTL with hysteresis; 5 V tolerant. INT 28 O interrupt output; programmable polarity (active HIGH or LOW) and signaling (edge or level triggered); CMOS output; 5 ns slew rate control. input; function determined by input MODE1 during power-up: MODE1 = 0 -- pin functions as ALE (address latch enable); a falling edge latches the address on the multiplexed address/data bus (AD[7:0]) MODE1 = 1 -- pin functions as A0 (address/data selection on AD[7:0]); a logic 1 detected on the rising edge of the WR pulse qualifies AD[7:0] as a register address; a logic 0 detected on the rising edge of the WR pulse qualifies AD[7:0] as a register data; used in Split Bus mode only. input pad; TTL; 5 V tolerant. ALE/A0 29 I AD0 30 I/O bit 0 of multiplexed address/data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. AD1 31 I/O bit 1 of multiplexed address/data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 7 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Pin description for LQFP64 ...continued Pin 32 Type[2] I/O Description bit 2 of multiplexed address/data bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. Table 2: Symbol[1] AD2 AD3 33 I/O bit 3 of multiplexed address/data bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. AD4 34 I/O bit 4 of multiplexed address/data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. AD5 35 I/O bit 5 of multiplexed address/data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DGND VCC(3.3) [3] 36 37 - digital ground supply voltage (3.3 V 0.3 V); supplies internal digital circuits or it is the tapped out voltage from the internal regulator; this regulated voltage cannot be used to drive external devices; see Section 10 bit 6 of multiplexed address/data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. AD6 38 I/O AD7 39 I/O bit 7 of multiplexed address/data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DATA0 40 I/O bit 0 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DATA1 41 I/O bit 1 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DGND VCC(3.3)[3] 42 43 - digital ground supply voltage (3.3 V 0.3 V); supplies internal digital circuits or it is the tapped out voltage from the internal regulator; this regulated voltage cannot be used to drive external devices; see Section 10 bit 2 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DATA2 44 I/O DATA3 45 I/O bit 3 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DATA4 46 I/O bit 4 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 8 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Pin description for LQFP64 ...continued Pin 47 Type[2] I/O Description bit 5 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. Table 2: Symbol[1] DATA5 DATA6 48 I/O bit 6 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DATA7 49 I/O bit 7 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DATA8 50 I/O bit 8 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DATA9 51 I/O bit 9 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DATA10 52 I/O bit 10 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DATA11 53 I/O bit 11 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DATA12 54 I/O bit 12 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DATA13 55 I/O bit 13 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DATA14 56 I/O bit 14 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. DATA15 57 I/O bit 15 of bidirectional data. bidirectional pad; push pull output; 5 ns slew rate control; TTL; 5 V tolerant. VCC(3.3)[3] 58 - supply voltage (3.3 V 0.3 V); supplies internal digital circuits or it is the tapped out voltage from the internal regulator; this regulated voltage cannot be used to drive external devices; see Section 10 crystal oscillator output (12 MHz); connect a fundamental parallel-resonant crystal; leave this pin open when using an external clock source on pin XTAL1 crystal oscillator input (12 MHz); connect a fundamental parallel-resonant crystal or an external clock source (leaving pin XTAL2 unconnected) digital ground XTAL2 59 O XTAL1 60 I DGND 61 - 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 9 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Pin description for LQFP64 ...continued Pin 62 Type[2] I Description wake-up input (edge triggered); a LOW-to-HIGH transition generates a remote wake-up from `suspend' state. input pad; TTL with hysteresis; with internal pull-down resistor; 5 V tolerant. Table 2: Symbol[1] WAKEUP TEST VCC(3.3)[3] 63 64 O - test output; this pin is used for test purposes only supply voltage (3.3 V 0.3 V); supplies internal digital circuits or it is the tapped out voltage from the internal regulator; this regulated voltage cannot be used to drive external devices; see Section 10 [1] [2] [3] [4] [5] Symbol names with an overscore (e.g. NAME) represent active LOW signals. All outputs and I/O pins can source 4 mA of current. Add a decoupling capacitor (0.1 F) to all the supply pins. For better EMI results, add a 0.01 F capacitor in parallel to the 0.1 F. The DMA bus is in three-state until a DMA command (see Section 9.4.1) is executed. The control signals are not three-state. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 10 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 7. Functional description The ISP1581 is a high-speed USB device controller. It implements the USB 2.0/1.1 physical layer, the packet protocol layer and maintains up to 16 USB endpoints concurrently (control IN and control OUT, 7 IN and 7 OUT configurable) along with Endpoint EP0setup, which is used to access the setup buffer. USB Chapter 9 protocol handling is executed by means of external firmware. The ISP1581 has a fast general-purpose interface for communication with most types of microcontrollers/processors. This Microcontroller Interface is configured by pins BUS_CONF, MODE1 and MODE0 to accommodate most interface types. Two bus configurations are available, selected via input BUS_CONF during power-up: * Generic Processor mode (BUS_CONF = 1): - AD[7:0]: 8-bit address bus (selects target register) - DATA[15:0]: 16-bit data bus (shared by processor and DMA) - Control signals: R/W and DS or RD and WR (selected via pin MODE0), CS - DMA interface (generic slave mode only): uses lines DATA[15:0] as data bus, DIOR and DIOW as dedicated read and write strobes. * Split Bus mode (BUS_CONF = 0): - AD[7:0]: 8-bit local microprocessor bus (multiplexed address/data) - DATA[15:0]: 16-bit DMA data bus - Control signals: CS, ALE or A0 (selected via pin MODE1), R/W and DS or RD and WR (selected via pin MODE0) - DMA interface (master or slave mode): uses DIOR and DIOW as dedicated read and write strobes. For high-bandwidth data transfer, the integrated DMA handler can be invoked to transfer data to/from external memory or devices. The DMA Interface can be configured by writing to the proper DMA registers (see Section 9.4). The ISP1581 supports high-speed USB 2.0 and full-speed USB 1.1 signaling. Detection of the USB signaling speed is done automatically. ISP1581 has 8 kbytes of internal FIFO memory, which is shared among the enabled USB endpoints. There are 7 IN endpoints, 7 OUT endpoints and 2 control endpoints that are a fixed 64 bytes long. Any of the 7 IN and 7 OUT endpoints can be separately enabled or disabled. The endpoint type (interrupt, isochronous or bulk) and packet size of these endpoints can be individually configured depending on the requirements of the application. Optional double buffering increases the data throughput of these data endpoints. The ISP1581 requires a single supply of 3.3 V or 5.0 V, depending on the I/O voltage. It has 5.0 V tolerant I/O pads and has an internal 3.3 V regulator for powering the analog transceiver. The ISP1581 operates on a 12 MHz crystal oscillator. An integrated 40x PLL clock multiplier generates the internal sampling clock of 480 MHz. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 11 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 7.1 USB 2.0 transceiver The analog transceiver interfaces directly to the USB cable via integrated termination resistors. The high-speed transceiver requires an external resistor (12.0 k 1%) between pin RREF and ground to ensure an accurate current mirror that is used to generate the USB 2.0 current drive. A full-speed transceiver is integrated as well. This makes the ISP1581 compliant with USB 2.0 and USB 1.1, supporting both the high-speed and full-speed physical layer. After automatic speed detection, the Philips Serial Interface Engine sets the transceiver to use either high-speed or full-speed signaling. 7.2 Philips Serial Interface Engine (SIE) The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit (de-)stuffing, CRC checking/generation, Packet IDentifier (PID) verification/generation, address recognition, handshake evaluation/generation. 7.3 Philips HS (High-Speed) Transceiver 7.3.1 Philips Parallel Interface Engine In the HS Transceiver, The Philips PIE interface uses a 16 bit Parallel bi-directional data interface. The functions of the HS (High-speed) module also include Bit-stuffing/De-stuffing and NRZI Encoding/Decoding logic. 7.3.2 Peripheral circuit To maintain a constant current driver for HS (High-Speed) transmit circuits and to bias other analog circuits, an internal band-gap reference circuit and RREF resistor are used to form the reference current. This circuit requires an external precision resistor (12.0 k 1%) connected to analog ground. 7.3.3 HS detection ISP1581 handles more than one electrical state (FS/HS) under the USB specification. When the USB cable is connected from the device to the host controller, at first the device ISP1581 defaults to the Full-speed (FS) state until it sees a bus reset from the host controller. During the bus reset, the device initiates a HS chirp to detect whether the host-controller supports USB 2.0 or USB 1.1. Chirping must be done with the pull-up resistor connected and the internal termination resistors disabled. If the HS handshake shows that there is a HS host connected, then ISP1581 switches to the HS state. In HS state, the ISP1581 observes the bus for periodic activity. If the bus remains inactive for 3 ms, the device switches to the FS state to check for an SE0(Single-ended zero) condition on the USB bus. If an SE0 condition is detected for the designated time window(100 s to 875 s, see section 7.1.7.6 of the USB specification Rev. 2.0), the ISP1581 switches to the HS chirp state again to do a HS detection handshake. Otherwise, the ISP1581 remains in the FS state adhering to the bus-suspend specification. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 12 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 7.4 Voltage regulators Two 5 V to 3.3 V voltage regulators are integrated on-chip to separately supply the analog transceiver and the internal logic. The output of these voltage regulators are termed as VCCA(3.3) and VCC(3.3) to distinguish them as being used for the analog block and the digital block, respectively. The pin VCCA(3.3) is also used to supply an external 1.5 k pull-up resistor on the D+ line. Remark: Pins VCCA(3.3) and VCC(3.3) cannot be used to supply external devices. 7.5 Memory Management Unit (MMU) and integrated RAM The MMU and the integrated RAM provide the conversion between the USB speed (full speed: 12 Mbit/s, high speed: 480 Mbit/s) and the Microcontroller Handler or the DMA Handler. The data from the USB Bus is stored in the integrated RAM, which is cleared only when the microcontroller has read/written all data from/to the corresponding endpoint buffer or when the DMA Handler has read/written all data from/to the endpoint buffer. The endpoint buffer can also be cleared forcibly by setting the CLBUF bit in the control function register. A total of 8 kbytes RAM is available for buffering. 7.6 SoftConnect The connection to the USB is established by pulling the D+ line (for full-speed devices) HIGH through a 1.5 k pull-up resistor. In the ISP1581 an external 1.5 k pull-up resistor must be connected between pins RPU and VCCA(3.3). The RPU pin connects the pull-up resistor to the D+ line, when bit SOFTCT in the Mode register is set (see Table 7). After a hardware reset the pull-up resistor is disconnected by default (SOFTCT = 0). Bit SOFTCT remains unchanged by a USB bus reset. 7.7 Microcontroller/Processor Interface and Microcontroller/Processor Handler The Microcontroller Interface allows direct interfacing to most microcontrollers. The interface is configured at power-up via inputs BUS_CONF, MODE1 and MODE0. When BUS_CONF is set to logic 1, the Microcontroller Interface switches to the Generic Processor mode in which AD[7:0] is the 8-bit address bus and DATA[15:0] is the separate 16-bit data bus. If BUS_CONF is made logic 0, the interface is in the Split Bus mode, where AD[7:0] is the local microprocessor bus (multiplexed address/data) and DATA[15:0] is solely used as the DMA bus. If pin MODE0 is set to logic 1, pins RD and WR are the read and write strobes (8051 style). If pin MODE0 is logic 0, pins R/W and DS pins represent the direction and data strobe (Motorola style). When pin MODE1 is made logic 0, ALE is used to latch the multiplexed address on pins AD[7:0]. If pin MODE1 is set to logic 1, A0 is used to indicate address or data. Pin MODE1 is only used in Split Bus mode: in Generic Processor mode it must be tied to VCC(5.0) (logic 1). The Microcontroller Handler allows the external microcontroller to access the register set in the Philips SIE as well as the DMA Handler. The initialization of the DMA configuration is done via the Microcontroller Handler. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 13 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 7.8 DMA Interface and DMA Handler The DMA block can be subdivided into two blocks: the DMA Handler and the DMA Interface. The firmware writes to the DMA Command register to start a DMA transfer (see Table 28). The command opcode determines whether a generic DMA, PIO, MDMA or UDMA transfer will start. The Handler interfaces to the same FIFO (internal RAM) as used by the USB core. Upon receiving the DMA Command, the DMA Handler directs the data from the internal RAM to the external DMA device or from the external DMA device to the internal RAM. The DMA Interface configures the timings and the DMA handshake. Data can be transferred either using DIOR and DIOW strobes or by the DACK and DREQ handshakes. The different DMA configurations are set up by writing to the DMA Configuration register (see Table 33 and Table 34). For an IDE-based storage interface, the applicable DMA modes are PIO (Parallel I/O), MDMA (Multi word DMA; ATA), and UDMA (Ultra DMA; ATA). For a generic DMA interface, the DMA modes that can be used are Generic DMA (Slave) and MDMA (Master). 7.9 System Controller The System Controller implements the USB power-down capabilities of the ISP1581. Registers are protected against data corruption during wake-up following a `resume' (from the `suspend' state) by locking the write access until an unlock code has been written in the "Unlock Device" register. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 14 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 8. Modes of operation The ISP1581 has two bus configuration modes, selected via pin BUS_CONF/DA0 at power-up: * Split Bus mode (BUS_CONF = 0): 8-bit multiplexed address/data bus and separate 8-bit/16-bit DMA bus * Generic Processor mode (BUS_CONF = 1); separate 8-bit address and 16-bit data bus Details of the bus configurations for each mode are given in Table 3. Typical interface circuits for each mode are given in Section 14. Table 3: Bus configuration modes PIO width AD[7:0] A[7:0] D[15:0] DMA width DMAWD = 0 DMAWD = 1 0 1 D[7:0] D[7:0] D[15:0] D[15:0] Split Bus mode: multiplexed address/data on pins AD[7:0]; separate 8/16-bit DMA bus on pins DATA[15:0] Generic Processor mode: separate 8-bit address on pins AD[7:0]; 16-bit data (PIO and DMA) on pins DATA[15:0] Description BUS_CONF 9. Register descriptions Table 4: Name Initialization registers Address Mode Interrupt Configuration Interrupt Enable DMA Configuration DMA Hardware Data flow registers Endpoint Index Control Function Data Port Buffer Length Endpoint MaxPacketSize Endpoint Type Short Packet endpoints endpoint endpoint endpoint endpoint endpoint endpoint 2C 28 20 1C 04 08 24 endpoint selection, data flow direction endpoint buffer management data access to endpoint FIFO packet size counter maximum packet size selects endpoint type: control, isochronous, bulk or interrupt short packet received on OUT endpoint 1 1 2 2 2 2 2 device device device device DMA controller DMA controller 00 0C 10 14 38 3C USB device address + enable power-down options, global interrupt enable, SoftConnect interrupt sources, trigger mode, output polarity interrupt source enabling see sub-section "DMA registers" see sub-section "DMA registers" 1 1 1 4 2 1 Register summary Destination Address (Hex) Description Size (bytes) 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 15 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Table 4: Name Register summary...continued Destination Address (Hex) 30 34 38 (byte 0) 39 (byte 1) Description Size (bytes) 1 4 DMA registers DMA Command DMA Transfer Counter DMA Configuration DMA controller DMA controller DMA controller controls all DMA transfers sets byte count for DMA Transfer sets GDMA configuration (counter enable, 1 burst length, data strobing, bus width) sets ATA configuration (IORDY enable, mode selection: ATA/UDMA/MDMA/PIO) 1 DMA Hardware 1F0 Task File 1F1Task File 1F2 Task File 1F3 Task File 1F4 Task File 1F5 Task File 1F6 Task File 1F7 Task File 3F6 Task File 3F7 Task File DMA Interrupt Reason DMA Interrupt Enable DMA Endpoint DMA Strobe Timing General registers Interrupt Chip ID Frame Number Scratch Unlock Device Test Mode DMA controller ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral ATAPI peripheral DMA controller DMA controller DMA controller DMA controller device device device device device PHY 3C 40 48 49 4A 4B 4C 4D 44 4E 4F 50 (byte 0) 51 (byte 1) 54 (byte 0) 55 (byte 1) 58 60 18 70 74 78 7C 84 endian type, master/slave selection, signal 1 polarity for DACK, DREQ, DIOW, DIOR single address word register: byte 0 (lower 2 byte) is accessed first IDE device access IDE device access IDE device access IDE device access IDE device access IDE device access IDE device access (write only; reading returns FFH) IDE device access IDE device access shows reason (source) for DMA interrupt enables DMA interrupt sources selects endpoint FIFO, data flow direction strobe duration in UDMA/MDMA mode shows interrupt sources product ID code and hardware version last successfully received Start Of Frame: lower byte (byte 0) is accessed first allows save/restore of firmware status during `suspend' direct setting of D+, D- states, loopback mode, internal transceiver test (PHY) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 3 2 2 re-enables register access after `suspend' 2 1 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 16 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 9.1 Register access Register access depends on the bus width used: * 8-bit bus: multi-byte registers are accessed lower byte (LSByte) first. * 16-bit bus: for single-byte registers the upper byte (MSByte) must be ignored. Endpoint specific registers are indexed via the Endpoint Index register. The target endpoint must be selected first, before accessing the following registers: * * * * * * Buffer Length Control Function Data Port Endpoint MaxPacketsize Endpoint Type Short Packet. Remark: All reserved bits are not implemented. The bus and bus reset values are not defined. Therefore, writing to these reserved bits will have no effect. 9.2 Initialization registers 9.2.1 Address register (address: 00H) This register is used to set the USB assigned address and enable the USB device. Table 5 shows the Address register bit allocation. The DEVEN and DEVADDR bits will be cleared whenever a bus reset, a power-on reset or a soft reset occurs. In response to the standard USB request SET_ADDRESS, the firmware must write the (enabled) device address to the Address register, followed by sending an empty packet to the host. The new device address is activated when the host acknowledges the empty packet. Table 5: Bit Symbol Reset Bus reset Access Address register: bit allocation 7 DEVEN 0 0 R/W Table 6: Bit 7 6 to 0 6 5 4 3 DEVADDR[6:0] 00H 00H R/W Endpoint Configuration register: bit description Symbol DEVEN DEVADDR[6:0] Description A logic 1 enables the device. This field specifies the USB device address. 2 1 0 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 17 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 9.2.2 Mode register (address: 0CH) This register consists of 1 byte (bit allocation: see Table 7). In 16-bit bus mode the upper byte is ignored. The Mode register controls the resume, suspend and wake-up behavior, interrupt activity, soft reset, clock signals and SoftConnect operation. Table 7: Bit Symbol Reset Bus reset Access Mode register: bit allocation 7 CLKAON 0 0 R/W 6 SNDRSU 0 0 R/W Table 8: Bit 7 5 GOSUSP 0 0 R/W 4 SFRESET 0 0 R/W 3 GLINTENA 0 unchanged R/W 2 WKUPCS 0 0 R/W 1 reserved 0 SOFTCT 0 unchanged R/W Mode register: bit description Symbol CLKAON Description Clock Always On: A logic 1 indicates that the internal clocks are always running even during `suspend' state. A logic 0 switches off the internal oscillator and PLL, when they are not needed. During `suspend' state, this bit must be set to logic 0 to meet the suspend current requirements. The clock is stopped after a delay of approximately 2 ms, following the setting of bit GOSUSP. Send Resume: Writing a logic 1 followed by a logic 0 will generate an upstream `resume' signal of 10 ms duration, after a 5 ms delay. Go Suspend: Writing a logic 1 followed by a logic 0 will activate `suspend' mode. Soft Reset: Writing a logic 1 followed by a logic 0 will enable a software-initiated reset to ISP1581. A soft reset is similar to a hardware-initiated reset (via the RESET pin). Global Interrupt Enable: A logic 1 enables all interrupts. Individual interrupts can be masked OFF by clearing the corresponding bits in the Interrupt Enable register. Bus reset value: unchanged. Wake-up on Chip Select: A logic 1 enables remote wake-up via a LOW level on input CS. reserved; must write logic 0 SoftConnect: A logic 1 enables the connection of the 1.5 k pull-up resistor on pin RPU to the D+ line. Bus reset value: unchanged. 6 SNDRSU 5 4 GOSUSP SFRESET 3 GLINTENA 2 1 0 WKUPCS SOFTCT 9.2.3 Interrupt Configuration register (address: 10H) This 1-byte register determines the behavior and polarity of the INT output. The bit allocation is shown in Table 9. When the USB SIE receives or generates a ACK, NAK or STALL, it will generate interrupts depending on three Debug mode bit fields: * CDBGMOD[1:0]: interrupts for the Control endpoint 0 * DDBGMODIN[1:0]: interrupts for the DATA IN endpoints 1 to 7 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 18 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device * DDBGMODOUT[1:0]: interrupts for the DATA OUT endpoints 1 to 7. The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow the user to individually configure when the ISP1581 will send an interrupt to the external microprocessor. Table 11 lists the available combinations. Bit INTPOL controls the signal polarity of the INT output (active HIGH or LOW, rising or falling edge). For level-triggering bit INTLVL must be made logic 0. By setting INTLVL to logic 1 an interrupt will generate a pulse of 60 ns (edge-triggering). Table 9: Bit Symbol Reset Bus reset Access Interrupt Configuration register: bit allocation 7 03H 03H R/W Table 10: Bit 7 to 6 5 to 4 3 to 2 1 6 5 03H 03H R/W 4 3 03H 03H R/W 2 1 INTLVL 0 unchanged R/W 0 INTPOL 0 unchanged R/W CDBGMOD[1:0] DDBGMODIN[1:0] DDBGMODOUT[1:0] Interrupt Configuration register: bit description Symbol CDBGMOD[1:0] DDBGMODIN[1:0] DDBGMODOUT[1:0] INTLVL Description Control 0 Debug Mode: values see Table 11 Data Debug Mode IN: values see Table 11 Data Debug Mode OUT: values see Table 11 Interrupt Level: selects the signaling mode on output INT (0 = level, 1 = pulsed). In pulsed mode an interrupt produces a 60 ns pulse. Bus reset value: unchanged. Interrupt Polarity: selects signal polarity on output INT (0 = active LOW, 1 = active HIGH). Bus reset value: unchanged. 0 INTPOL Table 11: Value 00H 01H 1XH [1] Debug mode settings CDBGMOD Interrupt on all ACK and NAK Interrupt on all ACK. Interrupt on all ACK and first NAK[1] DDBGMODIN Interrupt on all ACK and NAK Interrupt on ACK Interrupt on all ACK and first NAK[1] DDBGMODOUT Interrupt on all ACK, NYET and NAK Interrupt on ACK and NYET Interrupt on all ACK, NYET and first NAK[1] First NAK: the first NAK on an IN or OUT token after a previous ACK response. 9.2.4 Interrupt Enable register (address: 14H) This register enables/disables individual interrupt sources. The interrupt for each endpoint can be individually controlled via the associated IEPnRX or IEPnTX bits (`n' representing the endpoint number). All interrupts can be globally disabled via bit GLINTENA in the Mode Register (see Table 7). An interrupt is generated when the USB SIE receives or generates an ACK or NAK on the USB bus. The interrupt generation depends on the Debug mode settings of bit fields CDBGMOD, DDBGMODIN and DDBGMODOUT. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 19 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device All data IN transactions use the Transmit buffers (TX), which are handled by the DDBGMODIN bits. All data OUT transactions go via the Receive buffers (RX), which are handled by the DDBGMODOUT bits. Transactions on Control endpoint 0 (IN, OUT and SETUP) are handled by the CDBGMOD bits. Interrupts caused by events on the USB bus (SOF, Pseudo SOF, suspend, resume, bus reset, Setup and High Speed Status) can also be controlled individually. A bus reset disables all enabled interrupts except bit IEBRST (bus reset), which remains unchanged. The Interrupt Enable Register consists of 4 bytes. The bit allocation is given in Table 12. Table 12: Bit Symbol Reset Bus Reset Access Bit Symbol Reset Bus Reset Access Bit Symbol Reset Bus Reset Access Bit Symbol Reset Bus Reset Access R/W 23 IEP6TX 0 0 R/W 15 IEP2TX 0 0 R/W 7 reserved R/W R/W 22 IEP6RX 0 0 R/W 14 IEP2RX 0 0 R/W 6 IEDMA 0 0 R/W Table 13: Bit 31 to 26 25 to 12 11 10 9 8 7 R/W 21 IEP5TX 0 0 R/W 13 IEP1TX 0 0 R/W 5 IEHS_STA 0 0 R/W Interrupt Enable register: bit allocation 31 30 29 reserved R/W 20 IEP5RX 0 0 R/W 12 IEP1RX 0 0 R/W 4 IERESM 0 0 R/W R/W 19 IEP4TX 0 0 R/W 11 IEP0TX 0 0 R/W 3 IESUSP 0 0 R/W R/W 18 IEP4RX 0 0 R/W 10 IEP0RX 0 0 R/W 2 IEPSOF 0 0 R/W 28 27 26 25 IEP7TX 0 0 R/W 17 IEP3TX 0 0 R/W 9 reserved R/W 1 IESOF 0 0 R/W 24 IEP7RX 0 0 R/W 16 IEP3RX 0 0 R/W 8 IEP0SETUP 0 0 R/W 0 IEBRST 0 unchanged R/W Interrupt Enable register: bit description Symbol IEP7TX to IEP1RX IEP0TX IEP0RX IEP0SETUP Description reserved; must write logic 0 A logic 1 enables interrupt from the indicated endpoint. A logic 1 enables interrupt from the Control IN endpoint 0. A logic 1 enables interrupt from the Control OUT endpoint 0. reserved A logic 1 enables the interrupt for the Setup data received on endpoint 0. reserved 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 20 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Interrupt Enable register: bit description...continued Symbol IEDMA IEHS_STA IERESM IESUSP IEPSOF IESOF IEBRST Description A logic 1 enables interrupt upon DMA status change detection. A logic 1 enables interrupt upon detection of a High Speed Status change. A logic 1 enables interrupt upon detection of a `resume' state. A logic 1 enables interrupt upon detection of a `suspend' state. A logic 1 enables interrupt upon detection of a Pseudo SOF. A logic 1 enables interrupt upon detection of an SOF. A logic 1 enables interrupt upon detection of a bus reset. Table 13: Bit 6 5 4 3 2 1 0 9.2.5 DMA Configuration register (address: 38H) See Section 9.4.3. 9.2.6 DMA Hardware register (address: 3CH) See Section 9.4.4. 9.3 Data flow registers 9.3.1 Endpoint Index register (address: 2CH) The Endpoint Index register selects a target endpoint for register access by the microcontroller. The register consists of 1 byte and the bit allocation is shown in Table 14. The following registers are indexed: * * * * * * Endpoint MaxPacketsize Endpoint Type Buffer Length Data Port Short Packet Control Function. For example, to access the OUT data buffer of endpoint 1 via the Data Port register, the Endpoint Index register has to be written first with 02H. Table 14: Bit Symbol Reset Bus reset Access R/W R/W R/W Endpoint Index register: bit allocation 7 reserved 6 5 EP0SETUP 0 unchanged R/W R/W 4 3 00H 2 1 0 DIR 0 ENDPIDX[3:0] 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 21 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Endpoint Index register: bit description Symbol EP0SETUP Description reserved Selects the SETUP buffer for Endpoint 0: 0 -- EP0 data buffer 1 -- SETUP buffer. Must be logic 0 for access to other endpoints than Endpoint 0. Table 15: Bit 7 to 6 5 4 to 1 ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access of Buffer Length, Control Function, Data Port, Endpoint Type, MaxPacketSize and Short Packet. DIR Direction bit: Sets the target endpoint as IN or OUT endpoint: 0 -- target endpoint refers to OUT (RX) FIFO 1 -- target endpoint refers to IN (TX) FIFO. 0 Table 16: SETUP Data OUT Data IN Addressing of Endpoint 0 buffers EP0SETUP 1 0 0 ENDPIDX 00H 00H 00H DIR 0 0 1 Buffer name 9.3.2 Control Function register (address: 28H) The Control Function register is used to perform the buffer management on the endpoints. It consists of 1 byte and the bit configuration is given in Table 17.The register bits can stall, clear or validate any enabled data endpoint. Before accessing this register, the Endpoint Index register must be written first to specify the target endpoint. Table 17: Bit Symbol Reset Bus reset Access [1] Control Function register: bit allocation 7 R/W 6 reserved R/W R/W 5 4 CLBUF 0 0 R/W 3 VENDP 0 0 R/W 2 reserved R/W 1 STATUS[1] 0 0 R/W 0 STALL 0 0 R/W Only applicable for control IN/OUT. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 22 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Control Function register: bit description Symbol CLBUF Description reserved. Clear Buffer: A logic 1 clears the RX buffer of the indexed endpoint; the TX buffer is not affected. The RX buffer is cleared automatically once the endpoint is read completely. This bit is set only when it is necessary to forcefully clear the buffer. Validate Endpoint: A logic 1 validates the data in the TX FIFO of an IN endpoint for sending on the next IN token. In general, the endpoint is validated automatically when its FIFO byte count has reached the endpoint MaxPacketSize. This bit is set only when it is necessary to validate the endpoint with the FIFO byte count which is below the Endpoint MaxPacketSize. reserved Status Acknowledge: This bit controls the generation of ACK or NAK during the status stage of a SETUP transfer. It is automatically cleared upon completion of the status stage and upon receiving a SETUP token. 0 -- sends NAK 1 -- sends empty packet following IN token (host-to-device) or ACK following OUT token (device-to-host). Table 18: Bit 7 to 5 4 3 VENDP 2 1 STATUS 0 STALL Stall Endpoint: A logic 1 stalls the indexed endpoint. This bit is not applicable for isochronous transfers. Note: `Stalling' a data endpoint will confuse the Data Toggle bit about the stalled endpoint because the internal logic picks up from where it is stalled. Therefore, the Data Toggle bit must be reset by disabling and re-enabling the corresponding endpoint (by setting the bit `ENABLE' to 0 or 1 in the endpoint type register) to reset the PID. 9.3.3 Data Port register (address: 20H) This 2-byte register provides direct access for a microcontroller to the FIFO of the indexed endpoint. In case of an 8-bit bus the upper byte is not used. The bit allocation is shown in Table 19. Device to host (IN endpoint): After each write action an internal counter is auto-incremented (by 2 for a 16-bit access, by 1 for an 8-bit access) to the next location in the TX FIFO. When all bytes have been written (FIFO byte count = endpoint MaxPacketSize), the buffer is validated automatically. The data packet will then be sent on the next IN token. When it is necessary to validate the endpoint whose byte count is less than the MaxPacketSize, it can be done via the control function register (bit VENDP). Host to device (OUT endpoint): After each read action an internal counter is auto-decremented (by 2 for a 16-bit access, by 1 for an 8-bit access) to the next location in the RX FIFO. When all bytes have been read, the buffer contents are cleared automatically. A new data packet can then be received on the next OUT token. The buffer contents can also be cleared via the Control Function register (bit CLBUF), when it is necessary to forcefully clear the contents. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 23 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Remark: The buffer can be validated or cleared automatically by using the Buffer Length register (see Table 21). Table 19: Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Table 20: Bit 15 to 8 7 to 0 7 6 5 4 00H 00H R/W Data Port register: bit description Symbol DATAPORT[15:8] DATAPORT[7:0] Description data (upper byte); not used in 8-bit bus mode data (lower byte) Data Port register: bit allocation 15 14 13 12 00H 00H R/W 3 2 1 0 DATAPORT[7:0] 11 10 9 8 DATAPORT[15:8] 9.3.4 Buffer Length register (address: 1CH) This 2-byte register determines the current packet size (DATACOUNT) of the indexed endpoint FIFO. The bit allocation is given in Table 21. The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint MaxPacketSize register is written (see Table 22). A smaller value can be written when required. After a bus reset the Buffer Length register is made zero. IN endpoint: When writing bytes into TX FIFO, DATACOUNT is loaded with the total number of bytes to be sent. If DATACOUNT exceeds MaxPacketSize, the total bytes will be transmitted out in packets of MaxPacketSize. Each of these full-sized packets are auto-validated when the endpoint buffer is filled with a size equal to the maximum packet size. If the total byte count is not a factor of MaxPacketSize, the final packet will be a short packet. DATACOUNT will track total bytes, and also auto-validate the short packet. If the total byte count is a factor of MaxPacketSize, a final empty packet will be appended if bit NOEMPKT in the Endpoint Type register is cleared (see Table 24). Otherwise, (if bit NOEMPKT is set), data transfer is considered finished when the buffer is empty. OUT endpoint: The DATACOUNT value is automatically initialized to the number of data bytes sent by the host on each ACK. After reading DATACOUNT bytes from the RX buffer, the buffer is automatically cleared to allow the next packet to be received from the host. Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is output as the lower byte (LSByte). 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 24 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Table 21: Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Buffer Length register: bit allocation 15 14 13 12 00H 00H R/W 7 6 5 4 00H 00H R/W 3 2 1 0 DATACOUNT[7:0] 11 10 9 8 DATACOUNT[15:8] 9.3.5 Endpoint MaxPacketSize register (address: 04H) This register determines the maximum packet size for all endpoints except Control 0. The register contains 2 bytes and the bit allocation is given in Table 22. Each time the register is written, the Buffer Length registers of all endpoints are re-initialized to the FFOSZ field value. The NTRANS bits control the number of transactions allowed in a single micro-frame (for high-speed Isochronous and interrupt endpoints only). Table 22: Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Endpoint MaxPacketSize register: bit allocation 15 R/W 7 14 reserved R/W 6 R/W 5 4 FFOSZ[7:0] 00H 00H R/W Table 23: Bit 15 to 13 12 to 11 Endpoint MaxPacketSize register: bit description Symbol reserved NTRANS[1:0] Description reserved Number of Transactions (HS mode only): 0 -- 1 packet per microframe 1 -- 2 packets per microframe 2 -- 3 packets per microframe 3 -- reserved. These bits are applicable for Isochronous/interrupt transactions only. 10 to 0 FFOSZ[10:0] FIFO Size: Sets the FIFO size in bytes for the indexed endpoint. Applies to both HS and FS operation. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 13 12 00H 00H R/W 11 10 9 FFOSZ[10:8] 00H 00H R/W 8 NTRANS[1:0] 3 2 1 0 9397 750 09665 Product data Rev. 04 -- 18 July 2002 25 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 9.3.6 Endpoint Type register (address: 08H) This register sets the Endpoint type of the indexed endpoint: isochronous, bulk or interrupt. It also serves to enable the endpoint and configure it for double buffering. Automatic generation of an empty packet for a zero length TX buffer can be disabled via bit NOEMPKT. The register contains 2 bytes and the bit allocation is shown in Table 24. Table 24: Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Endpoint Type register: bit allocation 15 7 R/W 14 6 reserved R/W Table 25: Bit 15 to 5 4 R/W 13 5 12 reserved R/W 4 NOEMPKT 0 0 R/W 3 ENABLE 0 0 R/W 2 DBLBUF 0 0 R/W 1 00H 00H R/W 0 ENDPTYP[1:0] 11 10 9 8 Endpoint Type register: bit description Symbol reserved NOEMPKT Description reserved. No Empty Packet: A logic 0 causes an empty packet to be appended to the next IN token of the USB data, if the Buffer Length register or the Endpoint MaxPacketSize register is zero. A logic 1 disables this function. This bit is applicable only in DMA mode. Endpoint Enable: A logic 1 enables the FIFO of the indexed endpoint. The memory size is allocated as specified in the Endpoint MaxPacketSize register. A logic 0 disables the FIFO. Note: `Stalling' a data endpoint will confuse the Data Toggle bit on the stalled endpoint because the internal logic picks up from where it has stalled. Therefore, the Data Toggle bit must be reset by disabling and re-enabling the corresponding endpoint (by setting the bit `ENABLE' to 0 or 1 in the endpoint type register) to reset the PID. 3 ENABLE 2 1 to 0 DBLBUF ENDPTYP[1:0] Double Buffering: A logic 1 enables double buffering for the indexed endpoint. A logic 0 disables double buffering. Endpoint Type: These bits select the endpoint type as follows: 01H -- isochronous 02H -- bulk 03H -- interrupt. 9.3.7 Short Packet register (address: 24H) This register is reserved. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 26 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 9.4 DMA registers Two types of Generic DMA transfer and three types of IDE-specified transfer can be done by writing the proper opcode in the DMA Command Register. The control bits are given in Table 26 (Generic DMA transfers) and Table 27 (IDE-specified transfers). GDMA read/write (opcode = 00H/01H) -- Generic DMA Slave mode; Depending on the MODE[1:0] bit set in the DMA configuration register, either the DACK signal or the DIOR/DIOW signals are used to strobe the data. These signals are driven by the external DMA Controller. GDMA slave mode can operate in either counter mode or EOT only mode. In counter mode, the DIS_XFER_CNT bit in the DMA configuration register must be set to logic 0. The DMA transfer counter register must be programmed before any DMA command is issued. The DMA transfer counter is set by writing from the LSByte to the MSByte (address: 34H to 37H). The DMA transfer count is updated internally only after the MSByte has been written. Once the DMA transfer is started, the transfer counter starts decrementing and upon reaching `0', the DMA_XFER_OK bit is set and an interrupt is generated by the ISP1581. If the DMA master wants to terminate the DMA transfer, it can issue an EOT signal to the ISP1581. This EOT signal overrides the transfer counter and can terminate the DMA transfer at any time. In the EOT only mode, DIS_XFER_CNT has to be set to logic 1. Although the DMA transfer counter can still be programmed, it will not have any effect on the DMA transfer. DMA transfer will start once the DMA command is issued. Any of the following three ways will terminate this DMA transfer. * Detecting an external EOT * Detecting an internal EOT (short packet on an OUT token) * resetting the DMA There are basically 3 interrupts programmable to differentiate the method of DMA termination; namely, the INT_EOT, EXT_EOT and the DMA_XFER_OK bits in the DMA Interrupt Reason register. Refer to Table 53 for details. MDMA (Master) read/write (opcode = 06H/07H) -- Generic DMA Master mode; Depending on the MODE[1:0] bit set in the DMA configuration register, either the DACK signal or the DIOR/DIOW signals are used to strobe the data. these signals are driven by the ISP1581. In the Master mode, BURST[2:0],DIS_XFER_CNT in the DMA configuration register and the external EOT signal are not applicable. DMA transfer counter is always enabled and the DMA_XFER_OK bit is set to `1' once the counter reaches `0'. PIO read/write (opcode = 04H/05H) -- PIO mode for IDE transfers; the specification of this mode can be obtained from the ATA Specification Rev. 4. DIOR and DIOW are used as data strobes, IORDY can be used by the device to extend the PIO cycle. MDMA read/write (opcode = 06H/07H) -- Multi word DMA mode for IDE transfers; the specification of this mode can be obtained from the ATA Specification Rev. 4. DIOR and DIOW are used as data strobes, while DREQ and DACK serve as handshake signals. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 27 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device UDMA read/write (opcode = 02H/03H) -- Ultra DMA mode for IDE transfers; the specification of this mode can be obtained from the ATA Specification Rev. 4. Pins DA0 to DA2, CS0 and CS1 are used to select a device register for access. Control signals are mapped as follows: DREQ (= DMARQ), DACK (= DMACK), DIOW (= STOP), DIOR (= HDMARDY or HSTROBE), IORDY (= DSTROBE or DDMARDY). Table 26: Control bits for Generic DMA transfers Description Control bits GDMA read/write (opcode = 00H/01H) DMA Configuration register (see Table 33 and Table 34) BURST[2:0] MODE[1:0] WIDTH0 DIS_XFER_CNT ATA_MODE EOT_POL ENDIAN[1:0] ACK_POL, DREQ_POL, WRITE_POL, READ_POL MASTER determines the number of DMA cycles, during which pin DREQ is kept asserted determines the active read/write data strobe signals selects the DMA bus width: 8 or 16 bits disables the use of the DMA Transfer Counter set to logic 0 (non-ATA transfer) selects the polarity of the EOT signal determines whether the data is to be byte swapped or normal. Applicable only in 16 bit mode. select the polarity of the DMA handshake signals set to logic 0 (slave) DMA Hardware register (see Table 35 and Table 36) MDMA (Master) read/write (opcode = 06H/07H) DMA Configuration register (see Table 33 and Table 34) DMA_MODE[1:0] MODE[1:0] WIDTH DIS_XFER_CNT ATA_MODE EOT_POL ENDIAN[1:0] ACK_POL, DREQ_POL, WRITE_POL, READ_POL MASTER Table 27: determines the MDMA timings for the DIOR and DIOW strobes (value 03H is used for UDMA only) determines the active data strobe(s). selects the DMA bus width: 8 or 16 bits disables the use of the DMA Transfer Counter set to logic 1 (ATA transfer) input EOT is not used determines whether the data is to be byte swapped or normal. Applicable only in 16 bit mode. select the polarity of the DMA handshake signals set to logic 1 (master) Control bits for IDE-specified DMA transfers Description DMA Hardware register (see Table 35 and Table 36) Control bits PIO read/write (opcode = 04H/05H) DMA Configuration register (see Table 33 and Table 34) PIO_MODE[2:0] ATA_MODE selects the PIO mode; timings are ATA(PI) compatible set to logic 1 (ATA transfer) 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 28 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Control bits for IDE-specified DMA transfers...continued Description set to logic 0 Table 27: Control bits MASTER DMA Hardware register (see Table 35 and Table 36) MDMA read/write (opcode = 06H/07H) DMA Configuration register (see Table 33 and Table 34) DMA_MODE[1:0] ATA_MODE MASTER selects the MDMA mode; timings are ATA(PI) compatible set to logic 1 (ATA transfer) set to logic 0 DMA Hardware register (see Table 35 and Table 36) UDMA read/write (opcode = 02H/03H) DMA Configuration register (see Table 33 and Table 34) DMA_MODE[1:0] IGNORE_IORDY ATA_MODE MASTER selects the UDMA mode; timings are ATA(PI) compatible used to ignore the IORDY pin during transfer set to logic 1 (ATA transfer) set to logic 0 DMA Hardware register (see Table 35 and Table 36) Remark: The DMA bus defaults to three-state, until a DMA command is executed. All the other control signals are not three-stated. 9.4.1 DMA Command register (address: 30H) The DMA Command register is a 1-byte register that initiates all DMA transfer activity on the DMA Controller. The register is write-only: reading it will return FFH. Remark: The DMA bus will be in three-state until a DMA command is executed. Table 28: Bit Symbol Reset Bus reset Access Table 29: Bit 7:0 DMA Command register: bit allocation 7 6 5 4 FFH FFH W DMA Command register: bit description Symbol DMA_CMD[7:0] Description DMA command code, see Table 30. 3 2 1 0 DMA_CMD[7:0] 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 29 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device DMA commands Name GDMA Read Description Generic DMA IN token transfer (slave mode only): Data is transferred from the external DMA bus to the internal buffer. Strobe: DIOW by external DMA Controller. Generic DMA OUT token transfer (slave mode only): Data is transferred from the internal buffer to the external DMA bus. Strobe: DIOR by external DMA Controller. UDMA Read command: Data is transferred from the external DMA to the internal DMA bus. UDMA Write command: Data is transferred in UDMA mode from the internal buffer to the external DMA bus. PIO Read command for ATAPI device: Data is transferred in PIO mode from the external DMA bus to the internal buffer. Data transfer starts when IORDY is asserted. Inputs DREQ and DACK are ignored. PIO Write command for ATAPI device: Data is transferred in PIO mode from the internal buffer to the external DMA bus. Data transfer starts when IORDY is asserted. Inputs DREQ and DACK are ignored. Multiword DMA Read: Data is transferred from the external DMA bus to the internal buffer. Multiword DMA Write: Data is transferred from the internal buffer to the external DMA bus. Read at address 01F0H: Initiates a PIO Read cycle from Task File 1F0. Before issuing this command the task file byte count should be programmed at address 1F4H (LSB) and 1F5H (MSB). Poll BSY status bit for ATAPI device: Starts repeated PIO Read commands to poll the BSY status bit of the ATAPI device. When BSY = 0, polling is terminated and an interrupt is generated. Read Task Files: Reads all task file registers except 1F0H and 1F7H. When reading has been completed, an interrupt is generated. reserved Validate Buffer (for debugging only): Request from the microcontroller to validate the endpoint buffer following an ATA to USB data transfer. Clear Buffer: Request from the microcontroller to clear the endpoint buffer after a USB to ATA data transfer. Restart: Request from the microcontroller to move the buffer pointers to the beginning of the endpoint FIFO. Table 30: 00 Code (Hex) 01 GDMA Write 02 03 04 UDMA Read UDMA Write PIO Read[1] 05 PIO Write[1] 06 07 0A MDMA Read MDMA Write Read 1F0 0B Poll BSY 0C Read Task Files 0D 0E Validate Buffer 0F 10 Clear Buffer Restart 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 30 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device DMA commands...continued Name Reset DMA Description Reset DMA: Initializes the DMA core to its power-on reset state. Remark: When the DMA core is reset during the Reset DMA command, the DREQ, DACK, DIOW and DIOR handshake pins will be temporarily asserted. This can cause some confusion to the external DMA Controller. To prevent this from happening, start the external DMA Controller only after the DMA reset is done. 12 MDMA stop MDMA stop: This command immediately stops the MDMA data transfer. This is applicable for commands 06H and 07H only. reserved Table 30: 11 Code (Hex) 13 to FF [1] - PIO Read or Write that started using DMA Command Register only performs 16-bit transfer. 9.4.2 DMA Transfer Counter register (address: 34H) This 4-byte register is used to set up the total byte count of a DMA transfer (DMACR). It indicates the remaining number of bytes left for transfer. The bit allocation is given in Table 31. The transfer counter is used in DMA modes: PIO (commands: 04H, 05H), UDMA (commands: 02H, 03H), MDMA (commands: 06H, 07H) and GDMA (commands: 00H, 01H). A new value is written into the register starting with the lower byte (DMACR1) or the lower word (MSByte: DMACR2, LSByte: DMACR1). Internally, the transfer counter is initialized only after the last byte (DMACR4) has been written. In the GDMA Slave mode only, the transfer counter can be disabled via bit DIS_XFER_CNT in the DMA Configuration Register (see Table 33). In this case, input signal EOT can be used to terminate the DMA transfer when data is transferred from the external device to the host via IN tokens. The last packet in the FIFO is validated when pin EOT is asserted. Table 31: Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access DMA Transfer Counter register: bit allocation 31 30 29 28 00H 00H R/W 23 22 21 20 00H 00H R/W 19 18 17 16 DMACR3 = DMACR[23:16] 27 26 25 24 DMACR4 = DMACR[31:24] 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 31 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 14 13 12 00H 00H R/W 11 10 9 8 Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 15 DMACR2 = DMACR[15:8] 7 6 5 4 00H 00H R/W 3 2 1 0 DMACR1 = DMACR[7:0] Table 32: Bit 31 to 24 23 to 16 15 to 8 7 to 0 DMA Transfer Counter register: bit description Symbol DMACR4, DMACR[31:24] DMACR3, DMACR[23:16] DMACR2, DMACR[15:8] DMACR1, DMACR[7:0] Description DMA transfer counter byte 4 (MSB) DMA transfer counter byte 3 DMA transfer counter byte 2 DMA transfer counter byte 1 (LSB) 9.4.3 DMA Configuration register (address: 38H) This register defines the DMA configuration for the Generic DMA (GDMA) and the Ultra-DMA (UDMA) modes. The DMA Configuration register consists of 2 bytes. The bit allocation is given in Table 33. Table 33: Bit Symbol Reset DMA Configuration register: bit allocation 15 reserved R/W 7 DIS_ XFER_ CNT 0 0 R/W 14 IGNORE_ IORDY 0 0 R/W 6 13 ATA_ MODE 0 0 R/W 5 BURST[2:0] 4 12 11 10 9 PIO_MODE[2:0] 00H 00H R/W 3 MODE[1:0] 2 1 reserved 0 WIDTH 8 DMA_MODE[1:0] 00H 00H R/W Bus Reset Access Bit Symbol Reset Bus Reset Access 00H 00H R/W 00H 00H R/W R/W 1 1 R/W 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 32 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device DMA Configuration register: bit description Symbol IGNORE_IORDY ATA_MODE Description reserved A logic 1 ignores the IORDY input signal (UDMA mode only). A logic 1 configures the DMA core for ATA or MDMA mode. Used when issuing DMA commands 02H to 07H, 0AH and 0CH; also used when directly accessing task file registers. A logic 0 configures the DMA core for non-ATA mode. Used when issuing DMA commands 00H and 01H. Table 34: Bit 15 14 13 12 to 11 DMA_MODE[1:0] These bits affect the timing for UDMA and MDMA mode: 00H -- UDMA/MDMA mode 0: ATA(PI) compatible timings 01H -- UDMA/MDMA mode 1: ATA(PI) compatible timings 02H -- UDMA/MDMA mode 2: ATA(PI) compatible timings 03H -- MDMA mode 3: enables the DMA Strobe Timing register (see Table 37 and Table 38) for non-standard strobe durations; only used in MDMA mode. 10 to 8 PIO_MODE[2:0][3] These bits affect the PIO timing (see Table 80): 00H to 04H -- PIO mode 0 to 4: ATA(PI) compatible timings 05H to 07H -- reserved. 7 DIS_XFER_CNT A logic 1 disables the DMA Transfer Counter (see Table 31). The transfer counter can only be disabled in GDMA slave mode; in master mode the counter is always enabled. These bits select the DMA burst length and the DREQ timing (GDMA Slave mode only): 00H -- DREQ is asserted until the last byte/word is transferred or until the FIFO becomes full or empty 01H -- DREQ is asserted and negated for each byte/word transferred[1][2] 02H -- DREQ is asserted and negated for every 2 bytes/words transferred[1][2] 03H -- DREQ is asserted and negated for every 4 bytes/words transferred[1][2] 04H -- DREQ is asserted and negated for every 8 bytes/words transferred[1][2] 05H -- DREQ is asserted and negated for every 12 bytes/words transferred[1][2] 06H -- DREQ is asserted and negated for every 16 bytes/words transferred[1][2] 07H -- DREQ is asserted and negated for every 32 bytes/words transferred[1][2]. 6 to 4 BURST[2:0] 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 33 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device DMA Configuration register: bit description...continued Symbol MODE[1:0] Description These bits only affect the GDMA (slave) and MDMA (master) handshake signals: 00H -- DIOR (master) or DIOW (slave): strobes data from the DMA bus into the ISP1581; DIOW (master) or DIOR (slave): puts data from the ISP1581 on the DMA bus 01H -- DIOR (master) or DACK (slave) strobes the data from the DMA bus into the ISP1581; DACK (master) or DIOR (slave) puts the data from the ISP1581 on the DMA bus 02H -- DACK (master and slave) strobes the data from the DMA bus into the ISP1581 and also puts the data from the ISP1581 on the DMA bus (This mode is applicable only to 16-bit DMA; this mode cannot be used for 8-bit DMA.) 03H -- reserved. Table 34: Bit 3 to 2 1 0 WIDTH reserved This bit selects the DMA bus width for GDMA (slave) and MDMA (master): 0 -- 8-bit data bus 1 -- 16-bit data bus. [1] [2] [3] DREQ is asserted only if space (writing) or data (reading) is available in the FIFO. This process is stopped when the transfer FIFO becomes empty. PIO Read or Write that started using DMA Command Register only performs 16-bit transfer. 9.4.4 DMA Hardware register (address: 3CH) The DMA Hardware register consists of 1 byte. The bit allocation is shown in Table 35. This register determines the polarity of the bus control signals (EOT, DACK, DREQ, DIOR, DIOW) and the DMA mode (master or slave). It also controls whether the upper and lower parts of the data bus are swapped (bits ENDIAN[1:0]), for modes GDMA (slave) and MDMA (master) only. Table 35: Bit Symbol Reset Bus reset Access DMA Hardware register: bit allocation 7 6 5 EOT_ POL 0 0 R/W 4 MASTER 0 0 R/W 3 ACK_ POL 0 0 R/W 2 DREQ_ POL 1 1 R/W 1 WRITE_ POL 0 0 R/W 0 READ_ POL 0 0 R/W ENDIAN[1:0] 00H 00H R/W 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 34 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device DMA Hardware register: bit description Symbol ENDIAN[1:0] Description These bits determine whether the data bus is swapped between internal RAM and the DMA bus: This only applies for modes GDMA (slave) and MDMA (master). 00H -- normal data representation 16-bit bus: MSB on DATA[15:8], LSB on DATA[7:0] 01H -- swapped data representation 16-bit bus: MSB on DATA[7:0], LSB on DATA[15:8] 02H, 03H -- reserved. Note: while operating with 8 bit data bus, ENDIAN bits should be always set to 00H. Table 36: Bit 7 to 6 5 EOT_POL Selects the polarity of the End Of Transfer input (used in GDMA slave mode only): 0 -- EOT is active LOW 1 -- EOT is active HIGH. 4 MASTER Selects the DMA master/slave mode: 0 -- GDMA slave mode. 1 -- MDMA master mode. 3 ACK_POL Selects the DMA acknowledgement polarity: 0 -- DACK is active LOW 1 -- DACK is active HIGH. 2 DREQ_POL Selects the DMA request polarity: 0 -- DREQ is active LOW 1 -- DREQ is active HIGH. 1 WRITE_POL Selects the DIOW strobe polarity. 0 -- DIOW is active LOW 1 -- DIOW is active HIGH. 0 READ_POL Selects the DIOR strobe polarity. 0 -- DIOR is active LOW 1 -- DIOR is active HIGH. 9.4.5 DMA Strobe Timing register (address: 60H) This 1-byte register controls the strobe timings for the MDMA mode, when the DMA_MODE bits in the DMA Configuration register have been set to 03H. The bit allocation is given in Table 37. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 35 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Table 37: Bit Symbol Reset Bus reset Access DMA Strobe Timing register: bit allocation 7 R/W 6 reserved R/W Table 38: Bit 7 to 5 4 to 0 R/W 5 4 3 2 DMA_STROBE_CNT[4:0] 1FH 1FH R/W 1 0 DMA Strobe Timing register: bit description Symbol DMA_ STROBE_ CNT[4:0] Description reserved. These bits select the strobe duration for DMA_MODE = 03H (see Table 33). The strobe duration is (N+1) cycles[1], with N representing the value of DMA_STROBE_CNT (see Figure 3). [1] The cycle duration indicates the internal clock cycle (33.3 ns/cycle). x x (N + 1) cycles 004aaa125 Fig 3. Programmable strobe timing. 9.4.6 Task File registers (addresses: 40H to 4FH) These registers allow direct access to the internal registers of an ATAPI peripheral using PIO mode. The supported Task File registers and their functions are shown in Table 39. The correct peripheral register is automatically addressed via pins CS1, CS0, DA2, DA1 and DA0 (see Table 40). Table 39: 1F0 1F1 1F2 1F3 1F4 1F5 1F6 1F7 3F6 3F7 Task File register functions ATA function data (16-bits) error/feature sector count sector number/LBA[7:0] cylinder low/LBA[15:8] cylinder high/LBA[23:16] drive/head/LBA[27:24] command alternate status/command drive address ATAPI function data (16-bits) error/feature interrupt reason reserved cylinder low cylinder high drive select status/command alternate status/command reserved Address (Hex) 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 36 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device ATAPI peripheral register addressing CS1 H H H H H H H H L L CS0 L L L L L L L L H H DA2 L L L L H H H H H H DA1 L L H H L L H H H H DA0 L H L H L H L H L H Table 40: Task file 1F0 1F1 1F2 1F3 1F4 1F5 1F6 1F7 3F6 3F7 In 8-bit bus mode, the 16-bit Task File register 1F0 requires 2 consecutive write/read accesses before the proper PIO write/read is generated on the IDE interface. The first byte is always the lower byte (LSByte). Other task file registers can be accessed directly. Writing to Task File registers can be done in any order except for Task File register 1F7, which must be written last. Table 41: Task File register 1F0 (address: 40H): bit allocation CS1 = H, CS0 = L, DA2 = L, DA1 = L, DA0 = L. Bit Symbol Reset Bus reset Access Table 42: Task File register 1F1 (address: 48H): bit allocation CS1 = H, CS0 = L, DA2 = L, DA1 = L, DA0 = H. Bit Symbol Reset Bus reset Access Table 43: Task File register 1F2 (address: 49H): bit allocation CS1 = H, CS0 = L, DA2 = L, DA1 = H, DA0 = L. Bit Symbol Reset Bus reset Access 7 6 5 4 00H 00H R/W 3 2 1 0 sector count (ATA) or interrupt reason (ATAPI) 7 6 5 4 00H 00H R/W 3 2 1 0 error/feature (ATA or ATAPI) 7 6 5 4 00H 00H R/W 3 2 1 0 data (ATA or ATAPI) 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 37 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Table 44: Task File register 1F3 (address: 4AH): bit allocation CS1 = H, CS0 = L, DA2 = L, DA1 = H, DA0 = H. Bit Symbol Reset Bus reset Access 7 6 5 4 00H 00H R/W 3 2 1 0 sector number/LBA[7:0] (ATA), reserved (ATAPI) Table 45: Task File register 1F4 (address: 4BH): bit allocation CS1 = H, CS0 = L, DA2 = H, DA1 = L, DA0 = L. Bit Symbol Reset Bus reset Access 7 6 5 4 00H 00H R/W 3 2 1 0 cylinder low/LBA[15:8] (ATA) or cylinder low (ATAPI) Table 46: Task File register 1F5 (address: 4CH): bit allocation CS1 = H, CS0 = L, DA2 = H, DA1 = L, DA0 = H. Bit Symbol Reset Bus reset Access 7 6 5 4 00H 00H R/W 3 2 1 0 cylinder high/LBA[23:16] (ATA) or cylinder high (ATAPI) Table 47: Task File register 1F6 (address: 4DH): bit allocation CS1 = H, CS0 = L, DA2 = H, DA1 = H, DA0 = L. Bit Symbol Reset Bus reset Access Table 48: Task File register 1F7 (address: 44H): bit allocation CS1 = H, CS0 = L, DA2 = H, DA1 = H, DA0 = H. Bit Symbol Reset Bus reset Access [1] Task File register 1F7 is a write-only register; a read will return FFH. 7 6 5 4 00H 00H R/W 3 2 1 0 drive/head/LBA[27:24] (ATA) or drive (ATAPI) 7 6 5 4 00H 00H W 3 2 1 0 command (ATA) or status[1]/command (ATAPI) 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 38 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Table 49: Task File register 3F6 (address: 4EH): bit allocation CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = L. Bit Symbol Reset Bus reset Access Table 50: Task File register 3F7 (address: 4FH): bit allocation CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = H. Bit Symbol Reset Bus reset Access 7 6 5 4 00H 00H R/W 3 2 1 0 drive address (ATA) or reserved (ATAPI) 7 6 5 4 00H 00H R/W 3 2 1 0 alternate status/command (ATA or ATAPI) 9.4.7 DMA Interrupt Reason register (address: 50H) This 2-byte register shows the source(s) of a DMA interrupt. Each bit is refreshed after a DMA command has been executed. An interrupt source is cleared by writing a logic 1 to the corresponding bit. The bit allocation is given in Table 51. Table 51: Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access DMA Interrupt Reason register: bit allocation 15 14 reserved R/W 7 1F0_WF_E 0 0 R/W R/W 6 1F0_WF_F 0 0 R/W Table 52: Bit 12 15 to 13 ODD_IND R/W 5 1F0_RF_E 0 0 R/W 13 12 ODD_IND 0 0 R/W 4 READ_1F0 0 0 R/W 11 EXT_EOT 0 0 R/W 3 BSY_ DONE 0 0 R/W 10 INT_EOT 0 0 R/W 2 TF_RD_ DONE 0 0 R/W 9 INTRQ_ PENDING 0 0 R/W 1 CMD_ INTRQ_OK 0 0 R/W 8 DMA_ XFER_OK 0 0 R/W 0 reserved R/W DMA Interrupt Reason Register: bit description Symbol Description reserved A logic 1 indicates that the last packet with odd bytes has been transferred from the OUT token buffer to the DMA. This is applicable only for the OUT token data in the DMA slave mode. It has no meaning for the IN token data. Refer to the document Using the Odd Bit Indicator for DMA. A logic 1 indicates that an external EOT is detected. This is applicable only in GDMA slave mode. A logic 1 indicates that an internal EOT is detected. see Table 53. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 11 10 EXT_EOT INT_EOT 9397 750 09665 Product data Rev. 04 -- 18 July 2002 39 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device DMA Interrupt Reason Register: bit description...continued Symbol INTRQ_PENDING DMA_XFER_OK Description A logic 1 indicates that a pending interrupt was detected on pin INTRQ. A logic 1 indicates that the DMA transfer has been completed (DMA Transfer Counter has become zero). This bit is only used in GDMA (slave) mode and MDMA (master) mode. A logic 1 indicates that the 1F0 write FIFO is empty and the microcontroller can start writing data. A logic 1 indicates that the 1F0 write FIFO is full and the microcontroller must stop writing data. A logic 1 indicates that 1F0 read FIFO is empty and the microcontroller must stop reading data. A logic 1 indicates that 1F0 FIFO contains unread data and the microcontroller can start reading data. A logic 1 indicates that the BSY status bit has become zero and polling has been stopped. A logic 1 indicates that the Read Task Files command has been completed. A logic 1 indicates that all bytes from the FIFO have been transferred (DMA Transfer Count zero) and an interrupt on pin INTRQ was detected. reserved Internal EOT-Functional relation with DMA_XFER_OK bit DMA_XFER_OK Description 0 1 1 During the DMA transfer, there is a premature termination with short packet. DMA transfer is completed with short packet and the DMA transfer counter has reached `0'. DMA transfer is completed without any short packet and the DMA transfer counter has reached `0'. Table 52: Bit 9 8 7 6 5 4 3 2 1 1F0_WF_E 1F0_WF_F 1F0_RF_E READ_1F0 BSY_DONE TF_RD_DONE CMD_INTRQ_OK 0 Table 53: INT_EOT 1 1 0 - 9.4.8 DMA Interrupt Enable register (address: 54H) This 2-byte register controls the interrupt generation of the source bits in the DMA Interrupt Reason register (see Table 51). The bit allocation is given in Table 54. The bit descriptions are given in Table 52. A logic 1 enables interrupt generation. The values after a (bus) reset are logic 0 (disabled). Table 54: Bit Symbol Reset Bus reset Access DMA Interrupt Enable register: bit allocation 15 14 reserved R/W R/W R/W 13 12 IE_ODD _IND 0 0 R/W 11 IE_EXT_EOT 0 0 R/W 10 IE_INT_EOT 0 0 R/W 9 IE_INTRQ_ PENDING 0 0 R/W 8 IE_DMA_ XFER_OK 0 0 R/W 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 40 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 5 IE_1F0_ RF_E 0 0 R/W 4 IE_ READ_1F0 0 0 R/W 3 IE_BSY_ DONE 0 0 R/W 2 IE_TF_ RD_DONE 0 0 R/W 1 IE_CMD_ INTRQ_OK 0 0 R/W 0 reserved R/W Bit Symbol Reset Bus reset Access 7 IE_1F0_ WF_E 0 0 R/W 6 IE_1F0_ WF_F 0 0 R/W 9.4.9 DMA Endpoint register (address: 58H) This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA transfers. The bit allocation is given in Table 55. Table 55: Bit Symbol DMA Endpoint register: bit allocation 7 R/W 6 reserved R/W Table 56: Bit 7 to 4 3 to 1 0 R/W R/W 0 0 R/W 5 4 3 2 EPIDX[2:0] 0 0 R/W 0 0 R/W 1 0 DMADIR 0 0 R/W Power Reset Bus Reset Access DMA Endpoint register: bit description Symbol EPIDX[2:0] DMADIR Description reserved selects the indicated endpoint for DMA access 0 -- selects the RX/OUT FIFO for DMA read transfers 1 -- selects the TX/IN FIFO for DMA write transfers. The DMA Endpoint register must not reference the endpoint that is indexed by the Endpoint Index register (02CH) at any time. Doing so would result in data corruption. Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. However, if the DMA Endpoint register is pointed to an active endpoint, the firmware must not reference the same endpoint on the Endpoint Index register. 9.5 General registers 9.5.1 Interrupt register (address: 18H) The Interrupt register consists of 4 bytes. The bit allocation is given in Table 57. When a bit is set in the Interrupt register, this indicates that the hardware condition for an interrupt has occurred. When the Interrupt register content is non-zero, the INT output will be asserted. Upon detecting the interrupt, the external microprocessor must read the Interrupt register to determine the source of the interrupt. Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various bus states can generate an interrupt: Resume, Suspend, Pseudo-SOF, SOF and Bus Reset. The DMA Controller only has one interrupt bit: the source for a DMA interrupt is shown in the DMA Interrupt Reason register (see Table 51). Each interrupt bit can be individually cleared by writing a logic 1. The DMA interrupt bit can be cleared by writing a logic 1 to the related interrupt source bit in the DMA Interrupt Reason register and writing a logic 1 to the DMA bit of the interrupt register. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 41 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Table 57: Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Interrupt register: bit allocation 31 R/W 23 EP6TX 0 0 R/W 15 EP2TX 0 0 R/W 7 reserved R/W 30 R/W 22 EP6RX 0 0 R/W 14 EP2RX 0 0 R/W 6 DMA 0 0 R/W Table 58: Bit 31 to 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 29 reserved R/W 21 EP5TX 0 0 R/W 13 EP1TX 0 0 R/W 5 HS_STAT 0 0 R/W R/W 20 EP5RX 0 0 R/W 12 EP1RX 0 0 R/W 4 RESUME 0 0 R/W R/W 19 EP4TX 0 0 R/W 11 EP0TX 0 0 R/W 3 SUSP 0 0 R/W R/W 18 EP4RX 0 0 R/W 10 EP0RX 0 0 R/W 2 PSOF 0 0 R/W 28 27 26 25 EP7TX 0 0 R/W 17 EP3TX 0 0 R/W 9 reserved R/W 1 SOF 0 0 R/W 24 EP7RX 0 0 R/W 16 EP3RX 0 0 R/W 8 EP0SETUP 0 0 R/W 0 BRESET 0 unchanged R/W Interrupt register: bit description Symbol reserved EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX Description reserved; must write logic 0 A logic 1 indicates the Endpoint 7 TX buffer as interrupt source. A logic 1 indicates the Endpoint 7 RX buffer as interrupt source. A logic 1 indicates the Endpoint 6 TX buffer as interrupt source. A logic 1 indicates the Endpoint 6 RX buffer as interrupt source. A logic 1 indicates the Endpoint 5 TX buffer as interrupt source. A logic 1 indicates the Endpoint 5 RX buffer as interrupt source. A logic 1 indicates the Endpoint 4 TX buffer as interrupt source. A logic 1 indicates the Endpoint 4 RX buffer as interrupt source. A logic 1 indicates the Endpoint 3 TX buffer as interrupt source. A logic 1 indicates the Endpoint 3 RX buffer as interrupt source. A logic 1 indicates the Endpoint 2 TX buffer as interrupt source. A logic 1 indicates the Endpoint 2 RX buffer as interrupt source. A logic 1 indicates the Endpoint 1 TX buffer as interrupt source. A logic 1 indicates the Endpoint 1 RX buffer as interrupt source. A logic 1 indicates the Endpoint 0 data TX buffer as interrupt source. A logic 1 indicates the Endpoint 0 data RX buffer as interrupt source. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 42 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Interrupt register: bit description...continued Symbol reserved EP0SETUP reserved DMA HS_STAT Description reserved. A logic 1 indicates that a SETUP token was received on Endpoint 0. reserved. DMA status: A logic 1 indicates a change in the DMA Status register. High Speed Status:.A logic 1 indicates a change from FS to HS mode (HS connection). This bit is not set, when the system goes into a FS suspend. Resume status: A logic 1 indicates that a status change from `suspend' to `resume' (active) was detected. Suspend status: A logic 1 indicates that a status change from active to `suspend' was detected on the bus. Pseudo SOF interrupt: A logic 1 indicates that a Pseudo SOF or SOF was received. Pseudo SOF is an internally generated clock signal (FS: 1 ms period, HS: 125 s period) synchronized to the USB bus SOF/SOF. SOF interrupt: A logic 1 indicates that a SOF/SOF was received. Bus Reset: A logic 1 indicates that a USB bus reset was detected. Table 58: Bit 9 8 7 6 5 4 3 2 RESUME SUSP PSOF 1 0 SOF BRESET 9.5.2 Chip ID register (address: 70H) This read-only register contains the chip identification and the hardware version numbers. The firmware should check this information to determine the functions and features supported. The register contains 3 bytes and the bit allocation is shown in Table 59. Table 59: Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Chip ID register: bit allocation 23 22 21 20 15H 15H R 15 14 13 12 81H 81H R 7 6 5 4 30H 30H R 3 2 1 0 VERSION[7:0] 11 10 9 8 CHIPID[15:8] 19 18 17 16 CHIPID[23:16] 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 43 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Chip ID Register: bit description Symbol CHIPID[15:8] VERSION Description Chip ID: upper byte (81H) Version number (30H): The version number will be upgraded as and when there are new revisions with improved performance and functionality. CHIPID[23:16] Chip ID: lower byte (15H) Table 60: Bit 23 to 16 15 to 8 7 to 0 9.5.3 Frame Number register (address: 74H) This read-only register contains the frame number of the last successfully received Start Of Frame (SOF). The register contains 2 bytes and the bit allocation is given in Table 61. In case of 8-bit access the register content is returned lower byte first. Table 61: Bit Symbol Frame Number register: bit allocation 15 reserved R 7 R 6 5 14 13 12 MICROSOF[2:0] 00H 00H R 4 SOFR[7:0] 00H 00H R Table 62: Bit 13 to 11 10 to 0 Frame Number register: bit description Symbol MICROSOF[2:0] SOFR[10:0] Description microframe number frame number 3 2 11 10 9 SOFR[10:8] 00H 00H R 1 0 8 Power Reset Bus Reset Access Bit Symbol Power Reset Bus Reset Access 9.5.4 Scratch register (address: 78H) This 16-bit register can be used by the firmware to save and restore information, e.g. the device status before it enters the `suspend' state. The content of this register will not be altered by a bus reset. The bit allocation is given in Table 63. Table 63: Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 9397 750 09665 Scratch Register: bit allocation 15 14 13 12 SFIRH[7:0] 00H unchanged R/W 7 6 5 4 SFIRL[7:0] 00H unchanged R/W (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 11 10 9 8 3 2 1 0 Product data Rev. 04 -- 18 July 2002 44 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Scratch Information register: bit description Symbol SFIRH[7:0] SFIRL[7:0] Description scratch firmware information register (high byte) scratch firmware information register (low byte) Table 64: Bit 15 to 8 7 to 0 9.5.5 Unlock Device register (address: 7CH) In `suspend' state all the internal registers are write-protected to prevent data corruption by external devices during a `resume'. Register access for reading is not blocked. To re-enable the ISP1581 registers from the write-protected mode, the firmware must write a 2-byte unlock code (AA37H) into this register. The bit allocation of the Unlock Device register is given in Table 65. Table 65: Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Unlock Device register: bit allocation 15 14 13 12 11 10 9 8 ULCODE[15:8] = AAH not applicable not applicable W 7 6 5 4 3 2 1 0 ULCODE[7:0] = 37H not applicable not applicable W Table 66: Bit 15 to 0 Unlock Device register: bit description Symbol ULCODE[15:0] Description Writing data AA37H unlocks the internal registers and FIFOs for writing, following a `resume'. 9.5.6 Test Mode register (address: 84H) This 1-byte register allows the firmware to set the (D+, D-) lines to predetermined states for testing purposes. The bit allocation is given in Table 67. Remark: Only one bit can be set at a time. Table 67: Bit Symbol Reset Bus reset Access Test Mode register: bit allocation 7 FORCEHS 0 0 R/W R/W 6 reserved R/W 5 4 FORCEFS 0 0 R/W 3 PRBS 0 0 R/W 2 KSTATE 0 0 R/W 1 JSTATE 0 0 R/W 0 SE0_NAK 0 0 R/W 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 45 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Test Mode Register: bit description Symbol FORCEHS FORCEFS PRBS KSTATE JSTATE SE0_NAK Description A logic 1 forces the hardware to high-speed mode only and disables the chirp detection logic. reserved. A logic 1 forces the physical layer to full-speed mode only and disables the chirp detection logic. A logic 1 sets the (D+, D-) lines to toggle in a pre-determined random pattern. Writing a logic 1 sets the (D+, D-) lines to the K state. Writing a logic 1 sets the (D+, D-) lines to the J state. Writing a logic 1 sets the (D+, D-) lines to a HS quiescent state. The device only responds to a valid HS IN token with a NAK. Table 68: Bit 7[1] 6 to 5 4[1] 3[2] 2[2] 1[2] 0[2] [1] [2] Either FORCEHS or FORCEFS should be set to logic 1 at a time. Of the four bits (PRBS, KSTATE, JSTATE and SE0_NAK), only one bit must be set to logic 1 at a time. 10. Power supply The ISP1581 can be powered from 3.3 V or 5.0 V. If The ISP1581 is powered by VCC = 5.0 V, an integrated voltage regulator provides a 3.3 V supply voltage for the internal logic and the USB transceiver. For connection details, see Figure 4. The ISP1581 can also be operated from VCC = 3.3 V. In this case, the internal regulator is disabled and all the supply pins are connected to VCC. For connection details see Figure 5. ISP1581 2 4 24 37 43 58 64 VCC(5.0) VCCA(3.3) VCC(3.3) VCC(3.3) VCC(3.3) VCC(3.3) VCC(3.3) 10 F 0.01 F 0.01 F 0.1 F 004aaa014 5.0 V 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 10 F Fig 4. ISP1581 with 5.0 V supply. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 46 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device ISP1581 2 VCC(5.0) 4 VCCA(3.3) 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.1 F 0.1 F 0.1 F 0.1 F 0.01 F 0.1 F 0.1 F 3.3 V 10 F 24 VCC(3.3) 37 43 58 64 VCC(3.3) VCC(3.3) VCC(3.3) VCC(3.3) 10 F 0.01 F 0.1 F 004aaa015 Fig 5. ISP1581 with 3.3 V supply. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 47 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 11. Limiting values Table 69: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI Ilatchup Vesd Parameter supply voltage input voltage latchup current electrostatic discharge voltage VI < 0 or VI > VCC ILI < 1 A pins D+, D-, GND and VCC(5.0) other pins Tstg Ptot Table 70: Symbol VCC VI VI(AI/O) VO(od) Tamb storage temperature total power dissipation Recommended operating conditions Parameter supply voltage input voltage range input voltage on analog I/O pins (D+, D-) open-drain output pull-up voltage ambient temperature Conditions with voltage converter without voltage converter Min. 4.0 3.0 0 0 0 -40 Max 5.5 3.6 5.5 3.6 VCC +85 Unit V V V V V C 4000 V Conditions Min. -0.5 -0.5 Max +6.0 VCC + 0.5 100 Unit V V mA -60 - 2000 +150 770 V C mW 12. Static characteristics Table 71: Static characteristics; supply pins VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol VCCA(3.3) ICC ICC(susp) [1] Parameter regulated supply voltage operating supply current suspend supply current Conditions with voltage converter no pull-up on pin D+ Min. 3.0[1] - Typ 3.3 130 450 Max 3.6 - Unit V mA A In `suspend' mode the minimum voltage is 2.7 V. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 48 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Table 72: Static characteristics: digital pins VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Input levels VIL VIH Output levels VOL VOH ILI LOW-level output voltage HIGH-level output voltage input leakage current IOL = rated drive IOH = rated drive 2.6 0.4 5 V V A LOW-level input voltage HIGH-level input voltage 2.0 0.8 V V Parameter Conditions Min. Typ Max Unit Leakage current Table 73: Static characteristics: analog I/O pins (D+, D-)[1] VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Parameter Conditions Min. Typ Max Unit USB 1.1 transceiver (full-speed) Input levels (differential receiver) VDI VCM differential input sensitivity differential common mode voltage LOW-level input voltage HIGH-level input voltage hysteresis voltage LOW-level output voltage HIGH-level output voltage pull-up on D+ RL = 1.5 k to +3.6V pull-down on D+, D-; RL = 15 k to GND |VI(D+) - VI(D-)| includes VDI range 0.2 0.8 2.5 V V Input levels (single-ended receiver) VIL VIH Vhys Output levels VOL VOH 0 2.8 0.4 3.6 V V 2.0 0.4 0.8 0.7 V V V USB 2.0 transceiver (high-speed) Input levels (differential receiver) VHSSQ VHSDSC VHSDI VHSCM Output levels VHSOI VHSOL high-speed idle level output voltage (differential) high-speed LOW-level output voltage (differential) -10 -10 +10 +10 mV mV high-speed squelch detection threshold (differential) high-speed disconnect detection threshold (differential) high-speed differential input sensitivity high-speed data signaling common mode voltage range squelch detected no squelch detected disconnect detected disconnect not detected |VI(D+) - VI(D-)| 150 625 300 -50 100 525 +500 mV mV mV mV mV mV 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 49 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Table 73: Static characteristics: analog I/O pins (D+, D-)[1]...continued VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol VHSOH VCHIRPJ VCHIRPK Parameter high-speed HIGH-level output voltage (differential) chirp-J output voltage (differential) chirp-K output voltage (differential) three-state leakage current transceiver capacitance pin to GND [1] Conditions Min. 360 700 -900 Typ - Max 440 1100 -500 Unit mV mV mV [1] Leakage current ILZ Capacitance CIN Resistance ZDRV2[2] ZINP Termination VTERM termination voltage for pull-up resistor on pin RPU 3.0[3] 3.6 V driver output impedance for USB steady-state drive 2.0 and USB 1.1 input impedance 40.5 10 45 49.5 M 20 pF 10 A [1] [2] [3] HS termination resistor is disabled, and pull-up resistor is connected. Occurs only during reset when both hub and device are high-speed capable. Includes internal matching resistors on both D+ and D-. This tolerance range complies with USB specification 2.0. In the `suspend mode, the minimum voltage is 2.7 V. 13. Dynamic characteristics Table 74: Dynamic characteristics VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. Symbol Reset tW(RESET) fXTAL pulse width on input RESET crystal frequency crystal oscillator running 500 12 s MHz Crystal oscillator Parameter Conditions Min. Typ Max Unit Table 75: Dynamic characteristics: analog I/O pins (D+, D-)[1] VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; CL = 50 pF; RPU = 1.5 k on D+ to VTERM.; unless otherwise specified. Symbol Parameter Conditions Min. Typ Max Unit Driver characteristics Full-speed mode tFR tFF FRFM rise time fall time differential rise/fall time matching (tFR/tFF) CL = 50 pF; 10 to 90% of |VOH - VOL| CL = 50 pF; 90 to 10% of |VOH - VOL| [2] 4 4 90 - 20 20 111.11 ns ns % 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 50 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Table 75: Dynamic characteristics: analog I/O pins (D+, D-)[1]...continued VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C; CL = 50 pF; RPU = 1.5 k on D+ to VTERM.; unless otherwise specified. Symbol VCRS tHSR tHSF Parameter output signal crossover voltage high-speed differential rise time high-speed differential fall time with captive cable with captive cable Conditions [2][3] Min. 1.3 500 500 Typ - Max 2.0 - Unit V ps ps High-speed mode Data source timing Full-speed mode tFEOPT tFDEOP source EOP width see Figure 6 [3] [3] 160 -2 - 175 +5 ns ns source differential data-to-EOP see Figure 6 transition skew Receiver timing Full-speed mode tJR1 tJR2 tFEOPR tFST receiver data jitter tolerance to next transition see Figure 7 [3] -18.5 -9 82 - - +18.5 +9 14 ns ns ns ns receiver data jitter tolerance for see Figure 7 paired transitions receiver SE0 width accepted as EOP; see Figure 6 [3] [3] width of SE0 during differential rejected as EOP; transition see Figure 8 Test circuit: see Figure 37. Excluding the first transition from Idle state. Characterized only, not tested. Limits guaranteed by design. [3] [1] [2] [3] TPERIOD +3.3 V crossover point differential data lines crossover point extended 0V differential data to SE0/EOP skew N x TPERIOD + t DEOP source EOP width: t EOPT receiver EOP width: t EOPR MGR776 TPERIOD is the bit duration corresponding with the USB data rate. Full-speed timing symbols have a subscript prefix `F', low-speed timings a prefix `L'. Fig 6. Source differential data-to-EOP transition skew and EOP width. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 51 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device TPERIOD +3.3 V differential data lines 0V tJR consecutive transitions N x TPERIOD + t JR1 paired transitions N x TPERIOD + t JR2 tJR1 tJR2 MGR871 TPERIOD is the bit duration corresponding with the USB data rate. Fig 7. Receiver differential data jitter. tFST +3.3 V differential data lines VIH(min) 0V MGR872 Fig 8. Receiver SE0 width tolerance. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 52 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 13.1 Timing symbols Table 76: Symbol Time symbols t T Signal names A C D E G I L P Q R address; DMA acknowledge (DACK) clock; command data input; data chip enable output enable instruction (program memory content); input (general) address latch enable (ALE) program store enable (PSEN, active LOW); propagation delay data output read signal (RD, active LOW); read (action); DMA request (DREQ) S W chip select write signal (WR, active LOW); write (action); pulse width U Y Logic levels H L P S V X Z logic HIGH logic LOW stop, not active (OFF) start, active (ON) valid logic level invalid logic level high-impedance (floating, three-state) undefined output (general) time cycle time (periodic signal) Legend for timing characteristics Description 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 53 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 13.2 Register access timing 13.2.1 Generic Processor mode (BUS_CONF = 1) Tcy(RW) t WHSH t RHSH CS t WHAX t RHAX AD [7:0] t RLDV (read) DATA [15:0] t AVRL RD t AVWL (write) DATA [15:0] t I1VI2L WR (I2) t DVWH t WLWH 004aaa130 t RHDZ t RLRH t WHDZ Fig 9. ISP1581 register access timing: separate address and data buses (MODE0 = 1). Tcy(RW) t WHSH t RHSH CS t WHAX t RHAX AD [7:0] t RLDV (read) DATA [15:0] t AVWL (write) DATA [15:0] t I1VI2L DS (I2) t DVWH t WLWH t I2HI1X t WHDZ t RHDZ read R/W (I1) write 004aaa131 Fig 10. ISP1581 register access timing: separate address and data buses (MODE0 = 0). 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 54 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device RD/WR CS READY t RDY1 004aaa152 t RDY2 Fig 11. ISP1581 READY signal timing. Table 77: ISP1581 register access timing parameters: separate address and data buses = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C. Parameter RD LOW pulse width address set-up time before RD LOW address hold time after RD HIGH RD LOW to data valid delay RD HIGH to data outputs three-state delay RD HIGH to CS HIGH delay WR LOW pulse width address set-up time before WR LOW address hold time after WR HIGH data set-up time before WR HIGH data hold time after WR HIGH WR HIGH to CS HIGH delay read/write cycle time R/W set-up time before DS LOW R/W hold time after DS HIGH READY LOW to CS LOW delay READY HIGH to RD/WR HIGH of the last access Min >tRLDV 0 0 0 0 15 0 0 11 5 0 80 0 0 Max 26 15 3 91 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VCC Symbol Reading tRLRH tAVRL tRHAX tRLDV tRHDZ tRHSH Writing tWLWH tAVWL tWHAX tDVWH tWHDZ tWHSH General Tcy(RW) tI1VI2L tI2HI1X tRDY1 tRDY2 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 55 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 13.2.2 Split Bus mode (BUS_CONF = 0) Split Bus mode (BUS_CONF = 0, MODE1 = 0, MODE0 = 0/1) Tcy(RW) t WHSH CS (read) AD [7:0] address data t WHDZ (write) AD [7:0] address data t DVWH t WLWH t LLWL t LLI2L DS (I2) t I2HI1X R/W (I1) t AVLL t I1VLL ALE MGT498 Fig 12. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 0,MODE0 = 0). Tcy(RW) t WHSH CS t RLDV (read) AD [7:0] address t LLRL RD t WHDZ (write) AD [7:0] address data t DVWH t WLWH t RLRH data t RHSH t RHDZ t LLWL t LLI2L WR (I2) ALE t AVLL 004aaa132 Fig 13. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 0,MODE0 = 1). 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 56 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device ISP1581 register access timing parameters: multiplexed address/data bus (MODE1 = 0) = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C. Parameter RD LOW pulse width RD LOW to data valid delay RD HIGH to data outputs three-state delay RD HIGH to CS HIGH delay ALE LOW set-up time before RD LOW WR/DS LOW pulse width data set-up time before WR HIGH ALE LOW to WR/DS LOW delay data hold time after WR/DS HIGH WR/DS HIGH to CS HIGH delay read/write cycle time address set-up time before ALE LOW R/W set-up time before ALE LOW ALE LOW to DS LOW delay R/W hold time after DS HIGH Min >tRLDV 0 0 0 15 5 0 5 0 80 0 5 5 5 Max 25 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Table 78: VCC Symbol Reading tRLRH tRLDV tRHDZ tRHSH tLLRL Writing tWLWH tDVWH tLLWL tWHDZ tWHSH General Tcy(RW) tAVLL tI1VLL tLLI2L tI2HI1X 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 57 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Split Bus mode (BUS_CONF = 0, MODE1 = 1, MODE 0 = 0/1) t A0WL A0 Tcy(RW) t WHSH CS t RLDV (read) AD [7:0] address t RLRH RD t AVWH data t RHSH t RHDZ t WHRH WR t WHDZ (write) AD [7:0] address data t DVWH t WLWH WR (I2) t WHWH RD (I1) 004aaa011 Fig 14. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 0, MODE0 = 1). 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 58 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device t A0WL A0 Tcy(RW) t WHSH CS t RLDV (read) AD [7:0] address t RLRH R/W t AVWH DS t WHDZ (write) AD [7:0] address data t DVWH t WLWH DS (I2) t I2HI1X R/W (I1) t WHWH t WHRH data t RHSH t RHDZ 004aaa133 Fig 15. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 1, MODE0 = 0). 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 59 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device t A0WL A0 Tcy(RW) t WHSH CS t RLDV (read) AD [7:0] address t RLRH RD t AVWH data t RHSH t RHDZ t WHRH WR t WHDZ (write) AD [7:0] address data t DVWH t WLWH WR (I2) t WHWH RD (I1) 004aaa011 Fig 16. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 1, MODE0 = 1). Table 79: ISP1581 register access timing parameters: multiplexed address/data bus (MODE1 = 1) = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C. Parameter RD LOW to data valid delay RD HIGH to data outputs three-state delay RD HIGH to CS HIGH delay RD LOW pulse width WR/DS HIGH to RD HIGH delay A0 set-up time before WR/DS LOW address set-up time before WR/DS HIGH data set-up time before WR/DS HIGH data hold time after WR/DS HIGH WR/DS HIGH to CS HIGH delay WR/DS LOW pulse width WR/DS HIGH (address) to WR/DS HIGH (data) delay Min 0 0 >tRLDV 40 0 5 5 5 0 15 40 Max 26 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns VCC Symbol Reading tRLDV tRHDZ tRHSH tRLRH tWHRH Writing tA0WL tAVWH tDVWH tWHDZ tWHSH tWLWH tWHWH 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 60 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device ISP1581 register access timing parameters: multiplexed address/data bus (MODE1 = 1)...continued = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C. Parameter read/write cycle time R/W hold time after DS HIGH Min 80 5 Max Unit ns ns Table 79: VCC Symbol General Tcy(RW) tI2HI1X 13.3 DMA timing 13.3.1 PIO mode Tcy1 device (1) address valid t su1 t h1 DIOR, DIOW (4) t w1 (write) DATA [7:0] (2) t su2 (read) DATA [7:0] (2) t su3 t h3(min) t d2 t h2 t w2 IORDY (3a) HIGH t su4 IORDY (3b) t su5 IORDY (3c) t su4 t w3 MGT499 (1) The device address consists of signals CS1, CS0, DA2, DA1 and DA0. (2) The data bus width depends on the PIO access command used. Task File register access uses 8 bits (DATA[7:0]), except for Task File register 1F0 which uses 16 bits (DATA[15:0]). DMA commands 04H and 05H also use a 16-bit data bus. (3) The device can negate IORDY to extend the PIO cycle with wait states. The host determines whether or not to extend the current cycle after tsu4 following the assertion of DIOR or DIOW. The following three cases are distinguished: 1. Device keeps IORDY released (high-impedance): no wait state is generated. 2. Device negates IORDY during tsu4, but re-asserts IORDY before tsu4 expires: no wait state is generated. 3. Device negates IORDY during tsu4 and keeps IORDY negated for at least 5 ns after tsu4 expires: a wait state is generated. The cycle is completed as soon as IORDY is re-asserted. For extended read cycles (DIOR asserted), the read data on lines DATAn must be valid at td1 before IORDY is asserted. (4) DIOR and DIOW have a programmable polarity: shown here as active LOW signals. Fig 17. PIO mode timing. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 61 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Table 80: PIO mode timing parameters VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C. Symbol Tcy1(min) tsu1(min) tw1(min) tw2(min) tsu2(min) th2(min) tsu3(min) th3(min.) td2(max) th1(min) tsu4(min) tsu5(min) tw3(max) [1] Parameter read/write cycle time (minimum) address to DIOR/DIOW on set-up time (minimum) DIOR/DIOW pulse width (minimum) DIOR/DIOW recovery time (minimum) data set-up time before DIOW off (minimum) data hold time after DIOW off (minimum) data set-up time before DIOR on (minimum) data hold time after DIOR off (minimum) data to three-state delay after DIOR off (minimum) address hold time after DIOR/DIOW off (minimum) IORDY after DIOR/DIOW on set-up time (minimum) read data to IORDY HIGH set-up time (minimum) IORDY LOW pulse width (maximum) [3] [2] [1] [1] [1] Mode 0 600 70 165 60 30 50 5 30 20 35 0 1250 Mode 1 383 50 125 45 20 35 5 30 15 35 0 1250 Mode 2 240 30 100 30 15 20 5 30 10 35 0 1250 Mode 3 180 30 80 70 30 10 20 5 30 10 35 0 1250 Mode 4 120 25 70 25 20 10 20 5 30 10 35 0 1250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns [3] [2] [3] Tcy1 is the total cycle time, consisting of the command active time tw1and is the command recovery (= inactive) time tw2: Tcy1 = tw1 + tw2. The minimum timing requirements for Tcy1, tw1 and tw2 must all be met. Since Tcy1(min) is greater than the sum of tw1(min) and tw2(min), a host implementation must lengthen tw1 and/or tw2 to ensure that Tcy1 is equal to or greater than the value reported in the IDENTIFY DEVICE data. A device implementation shall support any legal host implementation. td2 specifies the time after DIOR is negated, when the data bus is no longer driven by the device (three-state). If IORDY is LOW at tsu4, the host waits until IORDY is made HIGH before the PIO cycle is completed. In that case, tsu5 must be met for reading (tsu3 does not apply). When IORDY is HIGH at tsu4, tsu3 must be met for reading (tsu5 does not apply). 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 62 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 13.3.2 GDMA slave mode DREQ (2) t su1 DACK (1) t su3 DIOR/DIOW (1) t d2 (read) DATA [15:0] t su2 (write) DATA [15:0] MGT500 t w1 Tcy1 t h1 t d1 t w2 t h2 t a1 t h3 DREQ is continuously asserted until the last transfer is done or the FIFO is full. Data strobes: DIOR (read), DIOW (write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 18. GDMA slave mode timing (BURST = 00H, MODE = 00H). DREQ (2) t su1 DACK (1) t d2 DIOR/DIOW (1) HIGH t h2 (read) DATA [15:0] t su2 (write) DATA [15:0] MGT501 t w1 Tcy1 t h1 t w2 t d1 t h3 DREQ is continuously asserted until the last transfer is done or the FIFO is full. Data strobe: DACK (read/write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 19. GDMA slave mode timing (BURST = 00H, MODE = 02H). 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 63 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device DREQ (2) t su1 DACK (1) t su3 t d2 DIOR/DIOW (1) t h2 (read) DATA [15:0] t su2 (write) DATA [15:0] MGT502 t w1 Tcy1 t d1 t h1 t a1 t h3 DREQ is asserted for every transfer. Data strobes: DIOR (read), DIOW (write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 20. GDMA slave mode timing (BURST = 01H, MODE = 00H). DREQ (2) t su1 DACK (1) t d2 DIOR/DIOW (1) HIGH t h2 (read) DATA [15:0] t su2 (write) DATA [15:0] MGT503 t w1 Tcy1 t d1 t h1 t w2 t h3 DREQ is asserted for every transfer. Data strobe: DACK (read/write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 21. GDMA slave mode timing (BURST = 01H, MODE = 02H). 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 64 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device DREQ (2) t su1 t w1 t w2 t h1 DACK (1) t su3 t d2 Tcy1 t d1 DIOR/DIOW (1) t h2 (read) DATA [15:0] t su2 (write) DATA [15:0] MGT504 t h3 DREQ is asserted once per N transfers (N is determined by the BURST value). Example shown here: N = 2. Data strobes: DIOR (read), DIOW (write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 22. GDMA slave mode timing (BURST > 01H, MODE = 00H). DREQ (2) t su1 DACK (1) t d2 DIOR/DIOW (1) HIGH t h2 (read) DATA [15:0] t su2 (write) DATA [15:0] MGT505 t w1 t w2 t h1 Tcy1 t d1 t h3 DREQ is asserted once per N transfers (N is determined by the BURST value). Example shown here: N = 2. Data strobe: DACK (read/write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 23. GDMA slave mode timing (BURST > 01H, MODE = 02H). 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 65 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device DIOR/DIOW (1) EOT(1) 36 ns (min) DREQ t h1 004aaa012 (1) Programmable polarity: shown as active LOW. Note: EOT should be valid for 36 ns (min.) when DIOR/DIOW is active. Fig 24. EOT timing in Split Bus mode. RD/WR EOT(1) 36 ns (min) DREQ t h1 004aaa013 (1) Programmable polarity: shown as active LOW. Note: EOT should be valid for 36 ns (min.) when RD/WR is active. Fig 25. EOT timing in Generic Processor mode. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 66 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Table 81: GDMA slave mode timing parameters VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C. Symbol Tcy1 tsu1 td1 th1 tw1 tw2 td2 th2 th3 tsu2 tsu3 ta1 Parameter read/write cycle time DREQ set-up time before first DACK on DREQ on delay after last strobe off DREQ hold time after last strobe on DIOR/DIOW pulse width DIOR/DIOW recovery time read data valid delay after strobe on read data hold time after strobe off write data hold time after strobe off write data set-up time before strobe off DACK setup time before DIOR/DIOW assertion DACK de-assertion after DIOR/DIOW de-assertion Min 78 10 33.33 0 39 36 1 10 0 0 Max 53 600 20 5 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns 13.3.3 MDMA mode DREQ (2) Tcy1 DACK (1) t su1 DIOR/DIOW (1) t d1 (write) DATA [15:0] t h3 (read) DATA [15:0] t su2 MGT506 t w1 t w2 t d2 t h1 t d3 t su2 t h2 (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH. Fig 26. MDMA master mode timing. Table 82: MDMA mode timing parameters VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C. Symbol Tcy1(min) tw1(min) td1(max) th3(min) 9397 750 09665 Parameter read/write cycle time (minimum)[1] (minimum)[1] DIOR/DIOW pulse width Mode 0 Mode 1 Mode 2 Unit 480 215 150 5 150 80 60 5 120 70 50 5 ns ns ns ns data valid delay after DIOR on (maximum) data hold time after DIOR off (minimum) (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 67 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Table 82: MDMA mode timing parameters...continued VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C. Symbol tsu2(min) th2(min) tsu1(min) th1(min) tw2(min) td2(max) td3(max) Parameter data set-up time before DIOR/DIOW off (minimum) Mode 0 Mode 1 Mode 2 Unit 100 30 15 0 5 50 50 40 40 25 20 10 0 5 25 25 35 35 25 ns ns ns ns ns ns ns ns ns data hold time after DIOW off (minimum) 20 DACK set-up time before DIOR/DIOW on 0 (minimum) DACK hold time after DIOR/DIOW off (minimum) DIOR recovery time (minimum)[1] DIOW recovery time (minimum)[1] DIOR on to DREQ off delay (maximum) DIOW on to DREQ off delay (maximum) DACK off to data lines three-state delay (maximum) 20 50 215 120 40 20 [1] Tcy1 is the total cycle time, consisting of the command active time tw1 and is the command recovery (= inactive) time tw2: Tcy1 = tw1 + tw2. The minimum timing requirements for Tcy1, tw1 and tw2 must all be met. Since Tcy1(min) is greater than the sum of tw1(min) and tw2(min), a host implementation must lengthen tw1 and/or tw2 to ensure that Tcy1 is equal to or greater than the value reported in the IDENTIFY DEVICE data. A device implementation shall support any legal host implementation. 13.3.4 UDMA mode Tcy1 t su1 DIOR (1) (sender) t h1 DATA [15:0] (1) (sender) t h2 IORDY (1) (receiver) t su2 t h2 t h1 Tcy1 t su1 t h1 t su2 t h2 DATA [15:0] (1) (receiver) MGT507 (1) DATA[15:0] and strobe signals at the receiver require some time to stabilize due to the settling time and propagation delay of the cable. Fig 27. UDMA timing: sustained synchronous burst. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 68 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device DREQ (drive) t d1 DACK (1) (host) t su3 DIOW (host) t su3 DIOR (host) t d11 IORDY (drive) t d4 DATA [15:0] (drive) t su3 DA [2:0] and CS [1:0] MGT508 t d6 t d13 t d6 t d13 t d5 t su1 t h1 (1) Programmable polarity: shown as active LOW. Fig 28. UDMA timing: drive initiating a burst for a read command. DREQ (drive) t d1 DACK (1) (host) t su3 DIOW (host) t d11 IORDY (drive) t su3 DIOR (host) t su1 DATA [15:0] (host) t su3 DA [2:0] and CS [1:0] MGT509 t d6 t d2 t d1 t h1 (1) Programmable polarity: shown as active LOW. Fig 29. UDMA timing: drive initiating a burst for a write command. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 69 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device t d7 DREQ (drive) DACK (1) (host) LOW t d7 DIOW (host) t d8 IORDY t d9 DIOR DATA [15:0] MGT510 (1) Programmable polarity: shown as active LOW. Fig 30. UDMA timing: receiver pausing a burst. DREQ (drive) t d3 DACK (1) (host) t d2 DIOW (host) t d2 DIOR (host) t d12 IORDY (drive) t d4 DATA [15:0] (drive) t d5 DA [2:0] and CS [1:0] MGT511 t h3 t h3 t d2 t d10 t su1 t h1 CRC t h3 (1) Programmable polarity: shown as active LOW. Fig 31. UDMA timing: drive terminating a burst during a read command. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 70 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device DREQ (drive) t h3 DACK (1) (host) t d2 DIOW (host) t d7 IORDY (drive) t d9 DIOR (host) t su1 DATA [15:0] (host) CRC t h3 DA [2:0] and CS [1:0] MGT512 t d3 t d10 t d2 t d3 t h3 t h1 (1) Programmable polarity: shown as active LOW. Fig 32. UDMA timing: drive terminating a burst during a write command. t d2 DREQ (drive) t d3 DACK (1) (host) t d7 DIOW (host) t h3 DIOR (host) t d9 IORDY (drive) t su1 DATA [15:0] (drive) CRC t h3 DA [2:0] and CS [1:0] MGT513 t d5 t d4 t h3 t d2 t d3 t d10 t h1 (1) Programmable polarity: shown as active LOW. Fig 33. UDMA timing: host terminating a burst during a read command. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 71 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device t d2 DREQ (drive) t d2 DACK (1) (host) t h3 DIOW (host) t d2 IORDY (drive) t d12 DIOR (host) t su1 DATA [15:0] (host) CRC t h3 DA [2:0] and CS [1:0] MGT514 t d3 t d10 t h3 t h1 (1) Programmable polarity: shown as active LOW. Fig 34. UDMA timing: host terminating a burst during a write command. Table 83: UDMA mode timing parameters VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C. Symbol Tcy1 tsu2 th2 tsu1 th1 td1 td2 td3 td4 td5 tsu3 th3 td6 td7 td8 Parameter read/write cycle time (from strobe edge to strobe edge) data set-up time at receiver data hold time at receiver data set-up time at sender data hold time at sender unlimited interlock limited interlock time[1] minimum[1] time[1] Mode 0 Min 114 15 5 70 6 0 0 20 20 0 20 20 20 160 Max 150 10 70 50 Mode 1 Min 75 10 5 48 6 0 0 20 20 0 20 20 20 125 Max 150 10 70 30 Mode 2 Min 55 7 5 34 6 0 0 20 20 0 20 20 20 100 Max 150 10 70 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit limited interlock time with data line drivers switch-off delay data line drivers switch-on delay (host) data line drivers switch-on delay (drive) control signal set-up time before DACK on control signal hold time after DACK off DACK on to control signal transition delay ready to paused delay strobe to ready delay to ensure a synchronous pause 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 72 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Table 83: UDMA mode timing parameters...continued VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = -40 to +85 C. Symbol td9 td10 td11 td12 td13 [1] Parameter ready to final strobe edge delay DACK off to IORDY high-Z delay DACK on to IORDY HIGH delay final strobe edge to DREQ off or DIOW on delay first strobe delay after control signal on 0 Mode 0 Min Max 75 20 230 0 Mode 1 Min Max 60 20 200 0 Mode 2 Min Max 50 20 170 Unit ns ns ns ns ns 50 0 50 0 50 0 Interlock time is the time allowed between an action by one agent and the following action by the other agent. An agent can be a sender or a receiver. Interlocking actions require a response signal from the other agent before processing can continue. 14. Application information address 8 data CPU 16 ISP1581 AD7 to AD0 DATA15 to DATA0 read strobe write strobe chip select (R/W)/RD DS/WR CS MGT515 Fig 35. Typical interface connections for Generic Processor mode. DATA [15:0] DREQ ISP1581 DMA DACK DIOW DIOR ALE/A0 address latch enable ALE INT (R/W)/RD DS/WR AD7 to AD0 address/data 8 interrupt read strobe write strobe WR INTn RD 8051 MICROCONTROLLER P0.7/AD7 to P0.0/AD0 MGT516 Fig 36. Typical interface connections for Split Bus mode (slave mode). 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 73 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 15. Test information The dynamic characteristics of the analog I/O ports (D+, D-) as listed in Table 75, were determined using the circuit shown in Figure 37. test point D.U.T 15 k CL 50 pF MGT495 In full-speed mode an internal 1.5 k pull-up resistor is connected to pin D+. Fig 37. Load impedance for D+ and D- pins (full-speed mode). 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 74 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 16. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 49 33 32 ZE e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3) e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 0o o 12.15 12.15 11.85 11.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC 136E10 JEDEC MS-026 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 Fig 38. LQFP64 package outline. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 75 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 17. Soldering 17.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 17.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C small/thin packages. 17.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 76 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 17.5 Package related soldering information Table 84: Package[1] BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[4], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO [1] [2] Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable[3] Reflow[2] suitable suitable suitable suitable suitable suitable not not recommended[4][5] recommended[6] [3] [4] [5] [6] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 77 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 18. Revision history Table 85: Rev Date 04 20020718 Revision history CPCN Description Product data (9397 750 09665) Modifications: * * * * * * * * * * * * * * * * * * * * * * 03 02 01 20020218 20001023 20001004 - Changed pin 63 to a TEST pin Table 2: modified the pin description for the 17, 18, 19, 20 and 21 pins Section 7.9: removed the second sentence and modified the third sentence Table 7 and Table 8: made bit 1 reserved Section 9.4.1: added a remark after the first paragraph Table 30: Added a remark to the bit 11 description Table 34: modified description for the MODE field Section 9.2.2 second paragraph: removed the last sentence Section 9.5.4: modified the last sentence Table 71: for ICC(susp), added 450 A in the `typ' column and removed it from the `max' column Table 73: changed the `min' value of VOH to 2.8 V Added the table note 4 to Table 75 Added Figure 11. Also, added the last two rows to Table 77 Section 13.3.2: added ta1, th3 and tw2. Added 600 ns as the max value of tW1 in Table 81 Also, modified Figure 18 to Figure 23 Figure 24 and Figure 25: added DREQ Added reference to bit descriptions in Section 9.4.8 Added table note 4 to `Table 2' Added table note 5 to `Table 2'. Added `Direct interface ATA/ATAPI peripheral' to Section 2 Added remark that "The DMA bus is three-state..." to Table 27 Removed Section 13.1 "High-speed signals" and all references to that section. Table 73 "Static characteristics: analog I/O pins (D+, D-)[1]" replaced with new table Preliminary data (9397 750 09233) Objective specification (9397 750 07648) Objective specification; 9397 750 07487) 9397 750 09665 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 78 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device 19. Data sheet status Data sheet status[1] Objective data Preliminary data Product status[2] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Product data Production [1] [2] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 20. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 22. Trademarks ACPI -- is an open industry specification for PC power management, co-developed by Intel Corp., Microsoft Corp. and Toshiba Jaz -- is a registered trademark of Iomega Corp. OnNow -- is a trademark of Microsoft Corp. SoftConnect -- is a trademark of Royal Philips Electronics Zip -- is a registered trademark of Iomega Corp. 21. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 09665 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 04 -- 18 July 2002 79 of 80 Philips Semiconductors ISP1581 USB 2.0 HS interface device Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.4 7.5 7.6 7.7 7.8 7.9 8 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . 11 USB 2.0 transceiver . . . . . . . . . . . . . . . . . . . . 12 Philips Serial Interface Engine (SIE). . . . . . . . 12 Philips HS (High-Speed) Transceiver . . . . . . . 12 Philips Parallel Interface Engine . . . . . . . . . . . 12 Peripheral circuit . . . . . . . . . . . . . . . . . . . . . . . 12 HS detection . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Voltage regulators. . . . . . . . . . . . . . . . . . . . . . 13 Memory Management Unit (MMU) and integrated RAM . . . . . . . . . . . . . . . . . . . . . . . 13 SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Microcontroller/Processor Interface and Microcontroller/Processor Handler . . . . . 13 DMA Interface and DMA Handler . . . . . . . . . . 14 System Controller . . . . . . . . . . . . . . . . . . . . . . 14 Modes of operation . . . . . . . . . . . . . . . . . . . . . 15 Register descriptions . . . . . . . . . . . . . . . . . . . 15 Register access . . . . . . . . . . . . . . . . . . . . . . . 17 Initialization registers . . . . . . . . . . . . . . . . . . . 17 Address register (address: 00H). . . . . . . . . . . 17 Mode register (address: 0CH) . . . . . . . . . . . . 18 Interrupt Configuration register (address: 10H) 18 Interrupt Enable register (address: 14H) . . . . 19 DMA Configuration register (address: 38H) . . 21 DMA Hardware register (address: 3CH). . . . . 21 Data flow registers . . . . . . . . . . . . . . . . . . . . . 21 Endpoint Index register (address: 2CH) . . . . . 21 Control Function register (address: 28H) . . . . 22 Data Port register (address: 20H). . . . . . . . . . 23 Buffer Length register (address: 1CH) . . . . . . 24 Endpoint MaxPacketSize register (address: 04H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Endpoint Type register (address: 08H) . . . . . . 26 Short Packet register (address: 24H) . . . . . . . 26 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . 27 DMA Command register (address: 30H) . . . . 29 DMA Transfer Counter register (address: 34H) 31 DMA Configuration register (address: 38H) . . 32 DMA Hardware register (address: 3CH). . . . . 34 DMA Strobe Timing register (address: 60H). . 35 9.4.6 9.4.7 9.4.8 9.4.9 9.5 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 9.5.6 10 11 12 13 13.1 13.2 13.2.1 13.2.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 14 15 16 17 17.1 17.2 17.3 17.4 17.5 18 19 20 21 22 Task File registers (addresses: 40H to 4FH) . 36 DMA Interrupt Reason register (address: 50H) 39 DMA Interrupt Enable register (address: 54H) 40 DMA Endpoint register (address: 58H) . . . . . 41 General registers . . . . . . . . . . . . . . . . . . . . . . 41 Interrupt register (address: 18H) . . . . . . . . . . 41 Chip ID register (address: 70H) . . . . . . . . . . . 43 Frame Number register (address: 74H) . . . . . 44 Scratch register (address: 78H) . . . . . . . . . . . 44 Unlock Device register (address: 7CH) . . . . . 45 Test Mode register (address: 84H) . . . . . . . . . 45 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 48 Static characteristics . . . . . . . . . . . . . . . . . . . 48 Dynamic characteristics . . . . . . . . . . . . . . . . . 50 Timing symbols . . . . . . . . . . . . . . . . . . . . . . . 53 Register access timing . . . . . . . . . . . . . . . . . 54 Generic Processor mode (BUS_CONF = 1) . 54 Split Bus mode (BUS_CONF = 0) . . . . . . . . . 56 DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PIO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 GDMA slave mode . . . . . . . . . . . . . . . . . . . . . 63 MDMA mode . . . . . . . . . . . . . . . . . . . . . . . . . 67 UDMA mode. . . . . . . . . . . . . . . . . . . . . . . . . . 68 Application information . . . . . . . . . . . . . . . . . 73 Test information. . . . . . . . . . . . . . . . . . . . . . . . 74 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 75 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 76 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 76 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 77 Package related soldering information . . . . . . 77 Revision history . . . . . . . . . . . . . . . . . . . . . . . 78 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 79 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 (c) Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 18 July 2002 Document order number: 9397 750 09665 |
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